• 전력전자학회논문지
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• 제24권6호
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• pp.406-410
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• 2019

Three-level (3L) DC-DC converters are appropriate for high-input-voltage applications. Although the voltage stress of TL converter switches can be reduced to half of the input voltage, the primary side has a large circulating current, which degrades efficiency. In this study, a dual half-bridge cascaded TL converter is presented to reduce this circulating current and thus decrease the conduction loss of the primary circuit. Moreover, the proposed converter can reduce the voltage stress of rectifier diodes, thereby reducing their conduction loss. Therefore, efficiency can be improved by reducing the conduction loss of the primary circuit and rectifier diodes.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(2)
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• pp.511-514
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• 2004

Proposed about new inverter that can use in PV system in this paper. Multi_level inverter that used inverter makes use of 4 transformers is basis, primary winding of each transformer voltage as can do step_up or step_down to appropriate voltage space tap lake. Put circuit that tap that turn in transformer connects properly according to inhibit signal that sense change of input voltage (output voltage of solar cell place) and transformer secondary voltage controls point of contact of relay so that get into fixed output voltage. As a result, can minimise relative harmonic content despite change width of input voltage are wide because number of output voltage level of multi_level inverter does not decrease. Because proposed circuit manufactures is easy and control is easy and is no burden of cost price rise economically, commercialization expected to do easily and this study examined propriety of action as that compose and experiments proposed circuit.

• 대한전자공학회논문지SD
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• 제43권6호
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• pp.9-17
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• 2006

SoC(System-On-Chip) 시스템에서 초 저전력 시스템을 구현하기 위한 dynamic voltage and frequency scaling (DVFS)알고리즘에 사용될 시스템 버스의 다중 코어 전압 레벨을 생성해주는 새로운 다계층(multi-level) 코어 전압용 high-speed level up/down Shifter 회로를 제안한다. 이 회로는 내부 회로군과 외부 회로군 사이에서 서로 다른 전압레벨을 조정 접속하는 I/O용 level up/down shifter interface 회로로도 동시에 사용된다. 제안하는 회로는 인터페이스 접속에서 불가피하게 발생하는 속도감쇄와 Duty Ratio 불안정 문제를 최소화하는 장점을 갖고 있다. 본 회로는 500MHz의 입력 주파수에서 $0.6V\sim1.6V$의 다중 코어 전압을 각 IP들에서 사용되는 전압레벨로, 또는 그 반대의 동작으로 서로 Up/Down 하도록 설계하였다 그리고 제안하는 I/O 용 회로의 level up shifter는 500MHz의 입력 주파수에서 내부 코어 용 level up shifter의 출력전압인 1.6V를 I/O 전압인 1.8V, 2.5V, 3.3V로 전압레벨을 상승 하도록 설계하였으며, level down shifter는 반대의 동작으로 1Ghz의 입력 주파수에서 동작하도록 설계하였다. 시뮬레이션 및 결과는 $0.35{\mu}m$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process 와 65nm CMOS model 변수를 이용한 Hspice를 통하여 검증하였다. 또한, 제안하는 회로의 지연시간 및 파워소모 분석과 동작 주파수에 비례한 출력 전압의 Duty ratio 왜곡에 대한 연구도 하였다.

• Journal of Power Electronics
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• 제14권3호
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• pp.478-487
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• 2014

This study presents a new interleaved three-level zero-voltage switching (ZVS) converter for high-voltage and high-current applications. Two circuit cells are operated with interleaved pulse-width modulation in the proposed converter to reduce the current ripple at the input and output sides, as well as to decrease the current rating of output inductors for high-load-current applications. Each circuit cell includes one half-bridge converter and one three-level converter at the primary side. At the secondary side, the transformer windings of two converters are connected in series to reduce the size of the output inductor or switching current in the output capacitor. Based on the three-level circuit topology, the voltage stress of power switches is clamped at $V_{in}/2$. Thus, MOSFETs with 500 V voltage rating can be used at 800 V input voltage converters. The output capacitance of the power switch and the leakage inductance (or external inductance) are resonant at the transition interval. Therefore, power switches can be turned on under ZVS. Finally, experiments verify the effectiveness of the proposed converter.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 추계학술대회 논문집
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• pp.267-270
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• 2003

In this paper, a new energy recovery circuit for AC PDP(Plasma Display Panel) is proposed to decrease a sustain voltage and voltage stress on switching elements. In the proposed circuit, two auxiliary capacitors are connected directly to the power source through switching elements and inductors when ground potential is supplied to the panel. Therefore, the voltage across auxiliary capacitors can be increased by turns over the half of the source voltage. Because the intrinsic capacitance of PDP is charged sufficiently from the auxiliary capacitors, the level of sustain voltage and the voltage stress on the switching devices are decreased. To verify the validity of the proposed energy recovery circuit, computer simulations using PSpice program are carried out.

• Journal of Power Electronics
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• 제14권1호
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• pp.30-39
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• 2014

This paper studies a new three-level pulse-width modulation (PWM) resonant converter for high input voltage and high load current applications. In order to use high frequency power MOSFETs for high input voltage applications, a three-level DC converter with two clamped diodes and a flying capacitor is adopted in the proposed circuit. For high load current applications, the secondary sides of the proposed converter are connected in parallel to reduce the size of the magnetic core and copper windings and to decrease the current rating of the rectifier diodes. In order to share the load current and reduce the switch counts, three resonant converters with the same active switches are adopted in the proposed circuit. Two transformers with a series connection in the primary side and a parallel connection in the secondary side are adopted in each converter to balance the secondary side currents. To overcome the drawback of a wide range of switching frequencies in conventional series resonant converters, the duty cycle control is adopted in the proposed circuit to achieve zero current switching (ZCS) turn-off for the rectifier diodes and zero voltage switching (ZVS) turn-on for the active switches. Finally, experimental results are provided to verify the effectiveness of the proposed converter.

• 조명전기설비학회논문지
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• 제13권4호
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• pp.134-141
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• 1999

본 논문은 전동차량용 전원장치의 출력전압 제어 안정성을 향상시키기 위한 연구이다. 입력전압 변동 및 부하 변동 등 과도상태시 출력 정전압 제어를 수행할 경우, L-C 필터부에서 공진이 발생함으로써 출력전압이 흔들리고 시스템이 불안해진다. 본 논문에서, 출력전압제어의 안정성을 확보하기 위해 주필터부에 공진을 억제하는 댐핑회로를 새롭게 제안하고, 이에 적합한 제어방법을 소개한다. 제안한 댐핑회로는 R-L로서 소형이고 간단히 구성된다. 제어기에는 과도상태분의 궤환제어와 대역저지필터를 적용한다. 또한 전력회로는 3레벨 PWM방식을 적용하였다. 이로서 과도상태에서 출력전압의 흔들림없이 변동폭을 10[%]이하로 제어할 수 있었으며, 정상상태의 출력 전압 왜형율도 3[%]이하로 감소시켰다.

• Journal of Power Electronics
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• 제15권3호
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• pp.652-659
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• 2015

This paper presents a new hybrid soft switching dc-dc converter with a low circulating current and high circuit efficiency. The proposed hybrid converter includes two sub-converters sharing two power switches. One is a three-level PWM converter and the other is a LLC converter. The LLC converter and the three-level converter share the lagging-leg switches and extend the zero-voltage switching (ZVS) range of the lagging-leg switches from nearly zero to full load since the LLC converter can be operated at f_sw (switching frequency) $\approx$ f_r (series resonant frequency). A passive snubber is used on the secondary side of the three-level converter to decrease the circulating current on the primary side, especially at high input voltage and full load conditions. Thus, the conduction losses due to the circulating current are reduced. The output sides of the two converters are connected in series. Energy can be transferred from the input voltage to the output load within the whole switching period. Finally, the effectiveness of the proposed converter is verified by experiments with a 1.44kW prototype circuit.

• Current Optics and Photonics
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• 제3권6호
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• pp.516-521
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• 2019

The electrical leakage levels of GaN-based light-emitting diodes (LEDs) containing leakage paths are estimated using photoluminescence (PL) and photovoltaic properties under photoexcitation conditions. The PL intensity and open-circuit voltage (V_OC) decrease because of carrier leakages depending on photoexcitation conditions when compared with reference values for typical LED chips without leakage paths. Changes of photovoltage-photocurrent characteristics and PL intensity due to carrier leakage are employed to assess the leakage current levels of LEDs with leakage paths. The current corresponding to the reduced V_OC of an LED with leakage from the photovoltaic curve of a reference LED without leakage is matched with the leakage current calculated using the PL intensity reduction ratio and short-circuit current of the LED with leakage. The current needed to increase the voltage for an LED with a leakage under photoexcitation from V_OC of the LED up to V_OC of a reference LED without a leakage is identical to the additional current needed for optical turn-on of the LED with a leakage. The leakage current level estimated using the PL and photovoltaic properties under photoexcitation is consistent with the leakage level measured from the voltage-current characteristic obtained under current injection conditions.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.876-879
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• 2002

A novel driving technology of PDP, which enables to decrease the sustain voltage of conventional technology by half without lowering the gas discharging voltage. This technology, realizable without much increased cost of the semiconductor devices, gives a significant improvement in the power efficiency, essential for the design of a drive circuit for PDP. A comparative analysis and experimental results are presented to show the validity of the proposed driving technology.