• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.6
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• pp.406-410
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• 2019

Three-level (3L) DC-DC converters are appropriate for high-input-voltage applications. Although the voltage stress of TL converter switches can be reduced to half of the input voltage, the primary side has a large circulating current, which degrades efficiency. In this study, a dual half-bridge cascaded TL converter is presented to reduce this circulating current and thus decrease the conduction loss of the primary circuit. Moreover, the proposed converter can reduce the voltage stress of rectifier diodes, thereby reducing their conduction loss. Therefore, efficiency can be improved by reducing the conduction loss of the primary circuit and rectifier diodes.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.511-514
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• 2004

Proposed about new inverter that can use in PV system in this paper. Multi_level inverter that used inverter makes use of 4 transformers is basis, primary winding of each transformer voltage as can do step_up or step_down to appropriate voltage space tap lake. Put circuit that tap that turn in transformer connects properly according to inhibit signal that sense change of input voltage (output voltage of solar cell place) and transformer secondary voltage controls point of contact of relay so that get into fixed output voltage. As a result, can minimise relative harmonic content despite change width of input voltage are wide because number of output voltage level of multi_level inverter does not decrease. Because proposed circuit manufactures is easy and control is easy and is no burden of cost price rise economically, commercialization expected to do easily and this study examined propriety of action as that compose and experiments proposed circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.9-17
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• 2006

We proposed a new High-speed CMOS Level Up/Down Shifter circuits that can be used with Dynamic Voltage and Frequency Scaling(DVFS) algorithm, for low power system in the SoC(System-on-Chip). This circuit used to interface between the other voltage levels in each CMOS circuit boundary, or between multiple core voltage levels in a system bus. Proposed circuit have advantage that decrease speed attenuation and duty ratio distortion problems for interface. The level up/down shifter of the proposed circuit designed that operated from multi core voltages$(0.6\sim1.6V)$ to used voltage level for each IP at the 500MHz input frequency The proposed circuit supports level up shifting from the input voltage levels, that are standard I/O voltages 1.8V, 2.5V, 3.3V, to multiple core voltage levels in between of $0.6V\sim1.6V$, that are used internally in the system. And level down shifter reverse operated at 1Ghz input frequency for same condition. Simulations results are shown to verify the proposed function by Hspice simulation, with $0.6V\sim1.6V$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process and $0.65{\mu}m$ CMOS model parameters. Moreover, it is researched delay time, power dissipation and duty ration distortion of the output voltage witch is proportional to the operating frequency for the proposed circuit.

• Journal of Power Electronics
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• v.14 no.3
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• pp.478-487
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• 2014

This study presents a new interleaved three-level zero-voltage switching (ZVS) converter for high-voltage and high-current applications. Two circuit cells are operated with interleaved pulse-width modulation in the proposed converter to reduce the current ripple at the input and output sides, as well as to decrease the current rating of output inductors for high-load-current applications. Each circuit cell includes one half-bridge converter and one three-level converter at the primary side. At the secondary side, the transformer windings of two converters are connected in series to reduce the size of the output inductor or switching current in the output capacitor. Based on the three-level circuit topology, the voltage stress of power switches is clamped at $V_{in}/2$. Thus, MOSFETs with 500 V voltage rating can be used at 800 V input voltage converters. The output capacitance of the power switch and the leakage inductance (or external inductance) are resonant at the transition interval. Therefore, power switches can be turned on under ZVS. Finally, experiments verify the effectiveness of the proposed converter.

• Proceedings of the KIPE Conference
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• 2003.11a
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• pp.267-270
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• 2003

In this paper, a new energy recovery circuit for AC PDP(Plasma Display Panel) is proposed to decrease a sustain voltage and voltage stress on switching elements. In the proposed circuit, two auxiliary capacitors are connected directly to the power source through switching elements and inductors when ground potential is supplied to the panel. Therefore, the voltage across auxiliary capacitors can be increased by turns over the half of the source voltage. Because the intrinsic capacitance of PDP is charged sufficiently from the auxiliary capacitors, the level of sustain voltage and the voltage stress on the switching devices are decreased. To verify the validity of the proposed energy recovery circuit, computer simulations using PSpice program are carried out.

• Journal of Power Electronics
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• v.14 no.1
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• pp.30-39
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• 2014

This paper studies a new three-level pulse-width modulation (PWM) resonant converter for high input voltage and high load current applications. In order to use high frequency power MOSFETs for high input voltage applications, a three-level DC converter with two clamped diodes and a flying capacitor is adopted in the proposed circuit. For high load current applications, the secondary sides of the proposed converter are connected in parallel to reduce the size of the magnetic core and copper windings and to decrease the current rating of the rectifier diodes. In order to share the load current and reduce the switch counts, three resonant converters with the same active switches are adopted in the proposed circuit. Two transformers with a series connection in the primary side and a parallel connection in the secondary side are adopted in each converter to balance the secondary side currents. To overcome the drawback of a wide range of switching frequencies in conventional series resonant converters, the duty cycle control is adopted in the proposed circuit to achieve zero current switching (ZCS) turn-off for the rectifier diodes and zero voltage switching (ZVS) turn-on for the active switches. Finally, experimental results are provided to verify the effectiveness of the proposed converter.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.13 no.4
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• pp.134-141
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• 1999

Ths paper describes on the stability improvement of output voltage control on the power suwJy for railway. On the transient states such as input voltage sudden change, the inpJt and output voltage beccxre unstable by L-C resonance occurred due to constant output voltage control. In this paper, the new clamping circuit for system stability is proposed, and control method using band attenuated filter and feed-forward terms is introduced. The propoesd damping circuit is composed with sma1l size R-L. Also, the 3 level PWM method is adopted to decrease distortion of output voltage. The output voltage is controlledl with variation under 10% without oscillation at transient states and have total hanmnic distortion under 3%.der 3%.

• Journal of Power Electronics
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• v.15 no.3
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• pp.652-659
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• 2015

This paper presents a new hybrid soft switching dc-dc converter with a low circulating current and high circuit efficiency. The proposed hybrid converter includes two sub-converters sharing two power switches. One is a three-level PWM converter and the other is a LLC converter. The LLC converter and the three-level converter share the lagging-leg switches and extend the zero-voltage switching (ZVS) range of the lagging-leg switches from nearly zero to full load since the LLC converter can be operated at f_sw (switching frequency) $\approx$ f_r (series resonant frequency). A passive snubber is used on the secondary side of the three-level converter to decrease the circulating current on the primary side, especially at high input voltage and full load conditions. Thus, the conduction losses due to the circulating current are reduced. The output sides of the two converters are connected in series. Energy can be transferred from the input voltage to the output load within the whole switching period. Finally, the effectiveness of the proposed converter is verified by experiments with a 1.44kW prototype circuit.

• Current Optics and Photonics
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• v.3 no.6
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• pp.516-521
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• 2019

The electrical leakage levels of GaN-based light-emitting diodes (LEDs) containing leakage paths are estimated using photoluminescence (PL) and photovoltaic properties under photoexcitation conditions. The PL intensity and open-circuit voltage (V_OC) decrease because of carrier leakages depending on photoexcitation conditions when compared with reference values for typical LED chips without leakage paths. Changes of photovoltage-photocurrent characteristics and PL intensity due to carrier leakage are employed to assess the leakage current levels of LEDs with leakage paths. The current corresponding to the reduced V_OC of an LED with leakage from the photovoltaic curve of a reference LED without leakage is matched with the leakage current calculated using the PL intensity reduction ratio and short-circuit current of the LED with leakage. The current needed to increase the voltage for an LED with a leakage under photoexcitation from V_OC of the LED up to V_OC of a reference LED without a leakage is identical to the additional current needed for optical turn-on of the LED with a leakage. The leakage current level estimated using the PL and photovoltaic properties under photoexcitation is consistent with the leakage level measured from the voltage-current characteristic obtained under current injection conditions.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.876-879
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• 2002

A novel driving technology of PDP, which enables to decrease the sustain voltage of conventional technology by half without lowering the gas discharging voltage. This technology, realizable without much increased cost of the semiconductor devices, gives a significant improvement in the power efficiency, essential for the design of a drive circuit for PDP. A comparative analysis and experimental results are presented to show the validity of the proposed driving technology.