• Journal of the Korean Society of Radiology
• /
• v.13 no.6
• /
• pp.831-840
• /
• 2019

The X-ray detector by liquid crystal with front light was proposed and verified by a X-ray image. The proposed detector utilizes the visible light instead of the electric signal by transistor. Therefore, it shows low noise and can be fabricated at low cost. The liquid crystal detector uses the orientation change of the liquid crystal molecule by conductivity change of the photoconductive layer. We can get the X-ray image from the transmitted light through the liquid crystal. The X-ray dose was calibrated from the measured transmittance of the visible light after comparison to the reference transmittance curve of the liquid crystal. The amorphous Se was used for photo con ducting layer and parylene was used for the liquid crystal alignment instead of the conventional alignment layer which needs high-temperature process over 200℃. The proposed X-ray detector can decrease the X-ray dose by high sensitivity which was verified by simulation. After the fabrication of the X-ray detector, the X-ray image was obtained as a function of the bias voltage to the liquid crystal. 10 lines/mm resolution was obtained from the line pattern and we will apply it to the 17inch diagonal liquid crystal X-ray detector with 3π retardation.

• Journal of the Korean Society of Radiology
• /
• v.4 no.2
• /
• pp.21-25
• /
• 2010

Recently, various semiconductor compounds as radiation detection material have been researched for a diagnostic x-ray detector application. In this paper, we have fabricated the CdS detecton sensor that has good photosensitivity and high x-ray absorption efficiency among other semiconductor compounds, and evaluated the application feasibility by investigating the detection properties about energy range of diagnostic x-ray generator. We have fabricated the line voltage selector(LCV) for a signal acquisition and quantities of CdS sensor, and designed the voltage detection circuit and rectifying circuit. Also, we have used a relative relation algorithm according to x-ray exposure condition, and fabricated the interface board with DAC controller. Performance evaluation was investigated by data processing using ANOVA program from voltage profile characteristics according to resistive change obtained by a tube voltage, tube current, and exposure time that is a exposure condition of x-ray generator. From experimental results, an error rates were reduced according to increasing of a tube voltage and tube current, and a good properties of 6%(at 90 kVp) and 0.4%(at 320 mA) ere showed. and coefficient of determination was 0.98 with relative relation of 1:1. The error rate according to x-ray exposure time showed exponential reduction because of delayed response velocity of CdS material, and the error rate has 2.3% at 320 msec. Finally, the error rate according to x-ray dose is below 10%, and a high relative relation was showed with coefficient of determination of 0.9898.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.15 no.6
• /
• pp.668-672
• /
• 2005

In this paper, a distance measuring system using a PSD sensor in proposed, which in suitable for low-cost localization sensor of a mobile robot. Because the distance-voltage output of PSD sensor has a non-linear property, the linearizing function is proposed through the experimental characteristics of the sensor. And the characteristics are tested and the distance-voltage data are measured in various colors and materials of object. The parameters of the proposed function are extracted by using the measured data. Finally, the performance and the accuracy of the developed system are verified according to the comparison of the distance by the proposed function with the real distance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.24 no.11
• /
• pp.1104-1112
• /
• 2013

This paper presents a wideband Colpitts voltage controlled oscillator(VCO) with nanosecond startup time and a center frequency of 8.35 GHz for a new bubble-type motion detector that has a bubble-layer detection zone at the specific distance from itself. The VCO circuit consists of two parts; one is a negative resistance part with a HEMT device and Colpitts feedback structure and the other is a resonator part with a varactor diode and shorted shunt microstrip line. The shorted shunt microstrip line and series capacitor are utilized to compensate for the input reactance of the packaged HEMT that changes from capacitive values to inductive values at 8.1 GHz due to parasitic package inductance. By tuning the feedback capacitors which determine negative resistance values, this paper also investigates startup time improvement with the negative resistance variation and tuning bandwidth improvement with the reactance slope variation of the negative resistance part. The VCO measurement shows the tuning bandwidth of 2.3 GHz(28 %), the output power of 4.1~7.5 dBm and the startup time of less than 2 nsec.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.4
• /
• pp.39-50
• /
• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.46 no.2
• /
• pp.72-77
• /
• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.9 no.1
• /
• pp.120-131
• /
• 2016

In this paper, a 512b MTP memory IP is designed by using MTP memory cells which are written by the FN (Fowler-Nordheim) tunneling method with only MV (medium voltage) devices of 5V which uses the back-gate bias, that is VNN (negative voltage). The used MTP cell consists of a CG (control gate) capacitor, a TG (tunnel gate) transistor, and a select transistor. To reduce the size of the MTP memory cell, just two PWs (P-wells) are used: one for the TG and the select transistors; and the other for the CG capacitor. In addition, just one DNW (deep N-well) is used for the entire 512b memory cell array. VPP and VNN generators supplying pumping voltages of ${\pm}8V$ which are insensitive to PVT variations since VPP and VNN level detectors are designed by a regulated voltage, V1V (=1V), provided by a BGR voltage generator.

• Progress in Medical Physics
• /
• v.15 no.2
• /
• pp.59-62
• /
• 2004

We developed very small parallel plate radiation detector by using our existing experience of mating radiation dosimeter and capability of analyzing characteristics of dosimeter. The radiation detector was consisted of microfilm and carbon electrode. The detector was parallel plate type of all-filled ionization chamber. The ionization chamber had been fabricated using an acrylic plate for the air cavity and carbon coated microfilm for electrical configuration. The alr gap between two electrodes was 0.48 mm. The diameters of collect electrode and guard electrode were 3.3 mm, 5 mm respectively. The diameter of high voltage electrode was 5 mm. Nominal sensitive volume of the chamber was 0.016 ㎤. The major parameters of the chamber characteristics such as leakage current, reproducibility, dose rate effect, and polarity effect were measured. The experimental results were as followings. Leakage current was 0.1 pA. Standard deviation of reproducibility was less than 0.1%. Dose rate effect was less than 1.5%. Polarity effect was less than 2.4%. These data were comparable to those of commercially available dosimetric system for QA-purpose. As the result, we found that the radiation detector consisting of the ionization chamber, microfilm and carbon electrode, was satisfactory for the purpose of the small field dosimetry in size and characteristics. In the future, We will try to refine the dosimeter for use in very small volume.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.7
• /
• pp.149-156
• /
• 2013

This paper presents a hardware edge detector of image signal at pixel level of CMOS image sensor (CIS). The circuit detects edges of an image based on a bump circuit combining with the pixels. The APS converts light into electrical signals and the bump circuit compares the brightness between the target pixel and its neighbor pixels. Each column on CIS 64 by 64 pixels array shares a comparator. The comparator decides a peak level of the target pixel comparing with a reference voltage. The proposed edge detector is implemented using 0.18um CMOS technology. The circuit shows higher fill factor 34% and power dissipation by 0.9uW per pixel at 1.8V supply.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.5
• /
• pp.77-86
• /
• 2016

This paper describes a dual-mode reference-less CDR(Clock Data Recovery) operating at full / half-rate and its operation algorithm. Proposed reference-less CDR consists of a frequency detector, a phase detector, a charge pump, a loop filter, a voltage controlled oscillator, and a digital block. The frequency and phase detectors operate at both full / half-rate for dual-mode operation and especially the frequency detector is capable of detecting the difference between data rate and clock frequency in the dead zone of general frequency detectors. Dual-mode reference-less CDR with the proposed algorithm can recover the data and clock within 1.2-1.3 us and operates reliably at both full-rate (2.7 Gb/s) and half-rate (5.4 Gb/s) with 0.5-UI input jitter.