• 한국콘텐츠학회논문지
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• 제21권7호
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• pp.157-163
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• 2021

파일 시스템에서 하나의 쓰기 연산은 여러 데이터를 수정할 수 있지만, 이러한 파일 시스템의 변경들은 원자적으로 디스크에 써지지 않는다. 따라서 파일 시스템의 일관성을 위해 기존의 저널링 기법은 시스템 성능을 저하시키는 대신 충돌 일관성을 보장한다. 비휘발성 메모리를 저널 공간으로 사용하면 비휘발성 메모리의 낮은 지연 시간과 바이트 수준 접근성으로 성능 저하를 완화시킬 수 있다고 알려졌다. 그러나 비휘발성 메모리를 고려한 저널링 기법 중에서 확장성을 제공하는 것은 없다. 본 논문에서는 확장적 저널링을 위해 비휘발성 메모리상의 저널 공간을 여러 영역으로 분할하여 한 영역에 집중된 연산을 분산시킨다. 또한, 저널 영역별로 입출력 쓰레드를 두어 저장 장치에 데이터 쓰기 연산을 가속화한다. 제안된 기법을 JFS에 적용하여 고성능 저장장치를 탑재한 멀티코어 서버에서 이를 평가한다. 평가 결과는 제안된 기법이 기존의 NVM 기반 저널링 파일 시스템의 기법보다 성능이 우수함을 보여준다.

• International Journal of Internet, Broadcasting and Communication
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• 제10권4호
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• pp.6-11
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• 2018

As embedded memory technology evolves, the traditional Static Random Access Memory (SRAM) technology has reached the end of development. For deepening the manufacturing process technology, the next generation memory technology is highly required because of the exponentially increasing leakage current of SRAM. Non-volatile memories such as STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory), PCM (Phase Change Memory) are good candidates for replacing SRAM technology in embedded memory systems. They have many advanced characteristics in the perspective of power consumption, leakage power, size (density) and latency. Nonetheless, nonvolatile memories have two major problems that hinder their use it the next-generation memory. First, the lifetime of the nonvolatile memory cell is limited by the number of write operations. Next, the write operation consumes more latency and power than the same size of the read operation.These disadvantages can be solved using the compiler. The disadvantage of non-volatile memory is in write operations. Therefore, when the compiler decides the layout of the data, it is solved by optimizing the write operation to allocate a lot of data to the SRAM. This study provides insights into how these compiler and architectural designs can be developed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.185-196
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• 2002

MRAM(magnetic random access memory) is a promising candidate for a universal memory with non-volatile, fast operation speed and low power consumption. The simplest architecture of MRAM cell is a combination of MTJ(magnetic tunnel junction) as a data storage part and MOS transistor as a data selection part. This article will review the general development status of MRAM and discuss the issues. The key issues of MRAM technology as a future memory candidate are resistance control and low current operation for small enough device size. Switching issues are controllable with a choice of appropriate shape and fine patterning process. The control of fabrication is rather important to realize an actual memory device for MRAM technology.

• Molecules and Cells
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• 제41권8호
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• pp.724-732
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• 2018

Plant defence responses to various biotic stresses via systemic acquired resistance (SAR) are induced by avirulent pathogens and chemical compounds, including certain plant hormones in volatile form, such as methyl salicylate and methyl jasmonate. SAR refers to the observation that, when a local part of a plant is exposed to elicitors, the entire plant exhibits a resistance response. In the natural environment, plants are continuously exposed to avirulent pathogens that induce SAR and volatile emissions affecting neighbouring plants as well as the plant itself. However, the underlying mechanism has not been intensively studied. In this study, we evaluated whether plants "memorise" the previous activation of plant immunity when exposed repeatedly to plant defensive volatiles such as methyl salicylate and methyl jasmonate. We hypothesised that stronger SAR responses would occur in plants treated with repeated applications of the volatile plant defence compound MeSA than in those exposed to a single or no treatment. Nicotiana benthamiana seedlings subjected to repeated applications of MeSA exhibited greater protection against Pseudomonas syringae pv. tabaci and Pectobacterium carotovorum subsp. carotovorum than the control. The increase in SAR capacity in response to repeated MeSA treatment was confirmed by analysing the defence priming of the expression of N. benthamiana Pathogenesis-Related 1a (NbPR1a) and NbPR2 by quantitative reverse-transcription PCR compared with the control. We propose the concept of plant memory of plant defence volatiles and suggest that SAR is strengthened by the repeated perception of volatile compounds in plants.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.192.1-192.1
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• 2015

We demonstrated the nonvolatile memory functionality of nano-crystalline silicon (nc-Si) and InGaZnOxide (IGZO) thin film transistors (TFTs) using mobile protons that are generated by very short time hydrogen neutral beam (H-NB) treatment in gate insulator (SiO2). The whole memory fabrication process kept under $50^{\circ}C$ (except SiO2 deposition process; $300^{\circ}C$). These devices exhibited reproducible hysteresis, reversible switching, and nonvolatile memory behaviors in comparison with those of the conventional FET devices. We also executed hydrogen treatment in order to figure out the difference of mobile proton generation between PECVD and H-NB CVD that we modified. Our study will further provide a vision of creating memory functionality and incorporating proton-based storage elements onto a probability of next generation flexible memorable electronics such as low power consumption flexible display panel.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.32-39
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• 2008

Tunnel oxide of non-volatile memory (NVM) devices would be very difficult to downscale if ten-year data retention were still needed. This requirement limits further improvement of device performance in terms of programming speed and operating voltages. Consequently, for low-power applications with Fowler-Nordheim programming such as NAND, program and erase voltages are essentially sustained at unacceptably high levels. A promising solution for tunnel oxide scaling is tunnel barrier engineering (TBE), which uses multiple dielectric stacks to enhance field-sensitivity. This allows for shorter writing/erasing times and/or lower operating voltages than single $SiO_2$ tunnel oxide without altering the ten-year data retention constraint. In this paper, two approaches for tunnel barrier engineering are compared: the crested barrier and variable oxide thickness. Key results of TBE and its applications for NVM are also addressed.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.101-101
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• 2007

We fabricated floating gate non-volatile memory devices with Si nanocrystals embedded in $SiN_x$ layer to achieve higher trap density. The average size of Si nanocrystals embedded in $SiN_x$ layer was ranging from 3 nm to 5 nm. The MOS capacitor and MOSFET devices with Si nanocrystals embedded in $SiN_x$ layer were analyzed the charging effects as a function of Si nanocrystals size.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.231-232
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• 2016

We have fabricated the nc-Si, IGZO based nonvolatile memory TFTs using mobile protons, which can be generated by simple hydrogen insertion process via H-NB treatment at room temperature. The TFT devices above exhibited reproducible hysteresis behavior, stable ON/OFF switching, and non-volatile memory characteristics. Also executed hydrogen treatment in order to figure out the difference of mobile proton generation between PECVD and our modified H-NB CVD. The room temperature proton-insertion process can reveal flexible inorganic based all-in-one display panel including driving circuit and memory circuit.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.103-104
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• 2006

PRAM (Phase change Random Access Memory) is one of the most promising candidates for next generation Non-volatile Memories. The Phase change material has been researched in the field of optical data storage media. However, the characteristics required in solid state memory are quite different from optical ones. In this study, the reset current and temperature profile of PRAM cells with bottom electrode were calculated by the numerical method.

• 반도체디스플레이기술학회지
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• 제22권3호
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• pp.106-111
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• 2023

The importance of load-to-use latency has been highlighted as state-of-the-art computing cores adopt deep pipelines and high clock frequencies. The cascaded cache was recently proposed to reduce the access cycle of the L1 cache by utilizing differences in latencies among banks of the cache structure. However, this study assumes the cache is comprised of SRAM, making it unsuitable for direct application to non-volatile memory-based systems. This paper proposes a novel mechanism and structure for lowering dynamic energy consumption. It inserts monitoring logic to keep track of swap operations and write counts. If the ratio of swap operations to total write counts surpasses a set threshold, the cache controller skips the swap of cache blocks, which leads to reducing write operations. To validate this approach, experiments are conducted on the non-volatile memory-based cascaded cache. The results show a reduction in write operations by an average of 16.7% with a negligible increase in latencies.