• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.12
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• pp.963-972
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• 1990

Burst errors is a major cause of the performance degradation of digital mobile radio communication over the Rayleigh fading channel. Convoluational codes with block interleaving can be employed to reduce the degredation. This paper has studied the randomness of errors and applied the interleaving to the Viterbi decoders of convolutional codes, Good interleavers for the r=3/4, L=7 convolution code has been searched through computer simulation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.11
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• pp.51-62
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• 2003

This paper presents a novel survivor memeory management and decoding techniques with sequential backward state transition control in the trace back Viterbi decoder. The Viterbi algorithm is an maximum likelihood decoding scheme to estimate the likelihood of encoder state for channel error detection and correction. This scheme is applied to a broad range of digital communication such as intersymbol interference removing and channel equalization. In order to achieve the area-efficiency VLSI chip design with high throughput in the Viterbi decoder in which recursive operation is implied, more research is required to obtain a simple systematic parallel ACS architecture and surviver memory management. As a method of solution to the problem, this paper addresses a progressive decoding algorithm with sequential backward state transition control in the trace back Viterbi decoder. Compared to the conventional trace back decoding techniques, the required total memory can be greatly reduced in the proposed method. Furthermore, the proposed method can be implemented with a simple pipelined structure with systolic array type architecture. The implementation of the peripheral logic circuit for the control of memory access is not required, and memory access bandwidth can be reduced Therefore, the proposed method has characteristics of high area-efficiency and low power consumption with high throughput. Finally, the examples of decoding results for the received data with channel noise and application result are provided to evaluate the efficiency of the proposed method.

• The Journal of Information Technology
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• v.3 no.1
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• pp.29-36
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• 2000

Viterbi decoder is a maximum likelihood decoding method for convolution coding used in satellite and mobile communications. In this paper, a Viterbi decoder with constraint length of K=7, 3 bit soft decision and traceback depth of ${\Gamma}=96$ for convolution code is implemented using VHDL. The hardware size of designed decoder is reduced by 4 bit pre-traceback in the survivor memory.

• Smart Media Journal
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• v.2 no.2
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• pp.39-43
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• 2013

In this paper, we suggest a new technique for WPC parity-check matrix (H-matrix) generation and a corresponding decoding process. The key idea is to construct WPC H-matrix by using a convolutional encoder. It is easy to have many different coderates from a mother code with convolutional codes. However, it is difficult to have many different coderates with LDPC codes. Constructing LDPC Hmatrix based on a convolutional code can easily bring the advantage of convolutional codes to have different coderates. Moreover, both LDPC and convolutional decoding algorithms can be applied altogether in the decoding part. This process prevents the performance degradation of short-length WPC code.

• The Transactions of the Korea Information Processing Society
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• v.7 no.6
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• pp.1923-1931
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• 2000

In this paper, e analyze the performance of the PSS-type Viterbi decoder which can reduce calculations and power consumption using the Monte Carlo simulations. Gaussian and burst noise channels are considered in this simulation, and we achieve that convolutional interleaver can reduce complexity and power consumption in burst noise channel. In order to implement the high-speed PSS-type Viterbi decoder, the architectures of decoder are presented, and we implemented the PSS-type Viterbi decoder for r=1/2, k=3 using the VHDL tool, and prove the decoding process.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.655-656
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• 2006

A parallel analog Viterbi decoder which decodes PR (1,2,2,1) signal of optical disc has been fabricated into chip. The proposed parallel analog Viterbi decoder implements the functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuits. In this paper, the analog parallel Viterbi decoding technology is applied for the PR signal. The benefit of analog processing is the low power consumption and the less silicon consumption. The test results of the fabricated chip are reported in this paper.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.1
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• pp.61-66
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• 2001

In this paper, we design high speed Viterbi decoding algorithm which is aimed for Wireless LAN. Wireless LAN transmits data at rate 6∼54 Mbps. This high speed is not easy to implement Viterbi decoder with single ACS. So parallel ACS butterfly structure is to be used and several time-dependent problem is to be solved. We simulate Viterbi algorithm using new branch metric calculating method to save time, and consider trace back algorithm which is adaptable to high speed Viterbi decoder. With simulated, we determine the structure of Viterbi decoder. This architecture is available to high speed and low power Viterbi decoder.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.251-257
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• 2014

The Viterbi algorithm(VA) is used to estimate the state transition of discrete-time finite state machine(FSM) that is in an uncorrelated noisy environment. This paper modified the Hamming Network to estimate the state transitions in the finite state machines, and proposed state-parallel and block-parallel Viterbi decoder. The modified Hamming Network(mHN) can perform the decoding of convolutional codes correctly as conventional Viterbi decoder. Furthermore, the complexities of the proposed Viterbi decoder are reduced approximately 10% less than conventional Viterbi decoder, and the processing times are improved approximately 40% more than conventional Viterbi decoder.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.8
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• pp.2077-2089
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• 1996

In this paper, a memory organization and its control method are proposed for the implementation of parallel Virterbi decoders. The design is mainly focused on lowering the hardware complexity of a parallel Viterbi decoder which is to reduce the decoding speed. The memories requeired in a Viterbi decoder are the SMM(State Metric Memory) and the TBM(Traceback Memory);the SMM for storing the path metrics of states and the TBM for storing the survial path information. A general parallel Viterbi decoder for high datarate usually consists of multiple ACS (Add-Compare-Select) units and their corresponding memeory modules.for parallel ACS units, SMMs and TBMs are partitioned into smaller independent pairs of memory modules which are separately interleaved to provide the maximum processing speed. In this design SMMs are controlled with addrss generators which can simultaneously compute addresses of the new path metrics. A bit shuffle technique is employed to provide a parallel access to the TBMs to store the survivor path informations from multiple ACS modules.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2006.11a
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• pp.161-164
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• 2006

이 논문에서는 AT-DMB (advanced terrestrial digital multimedia broadcasting) 시스템에서 채널정보를 이용하여 Viterbi 복호기의 성능을 향상시키는 방법을 제시하고 그 성능을 살펴보았다. 채널정보는 부반송파를 16-QAM 계층변조한 수신신호로부터 자력적으로 추정한다. 모의실험을 통해 채널정보를 이용한 Viterbi 복호기가 채널정보를 이용하지 않는 복호기에 비해 약 1 dB의 성능향상을 나타냄을 알 수 있었다.