• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.15 no.1
• /
• pp.21-28
• /
• 2004

In this paper we apply block turbo coding at the transmitter and iterative decoding algorithm at the receiver for different operating modes, based on the 5 ㎓ IEEE 802.1 la WLAN system, instead of convolutional coding and soft decision viterbi algorithm to improve forward error correcting performance. Experimental results showed that each coding scheme outperforms coding gains of up to 3.5 ㏈ at the BER of 10$\^$-3/.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.7B
• /
• pp.1393-1399
• /
• 1999

In this paper, a VLSI design of the convolutional codec chip of code rate r=l/3, and constraint length K=9 is presented, which is able to correct errors of the received data when transmitted data is corrupted in channels. The circuit design mainly aimed for simple implementation. In the decoder, Viterbi algorithm with 3-bit soft-decision is employed. For information sequence updating and storage, the register exchange method is employed, where the register length is 5$\times$K(45 stages). The codec chip is designed using VHDL language and Design Analyzer and VHDL Simulator of Synopsys are used for simulation and synthesis. The chip is composed of ENCODER block, ALIGN block, BMC block, ACS block, SEL_MIN block and REG_EXCH block. The operation of the codec chip is verified though the logic simulations, where several error conditions are assumed. As a result of the timing simulation after synthesis, the decoding speed of 325.5Kbps is achieved, and 6,894 gates is used.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.3A
• /
• pp.217-225
• /
• 2005

This paper presents specialized DSP instructions and their architecture for the Viterbi algorithm used in various wireless communication standards. The proposed architecture can significantly reduce the Trace Back (TB) latency. The proposed instructions perform the Add Compare Select (ACS) and TB operations in parallel and the architecture has special hardware, called the Offset Calculation Unit (OCU), which automatically calculates data addresses for the trellis butterfly computations. Logic synthesis has been Performed using the Samsung SEC 0.18 μm standard cell library. OCU consists of 1,460 gates and the maximum delay of OCU is about 5.75 ns. The BER performance of the ACS-TB parallel method increases about 0.00022dB at 6dB Eb/No compared with the typical TB method, which is negligible. When the constraint length K is 5, the proposed DSP architecture can reduce the decoding cycles about 17% compared with the Carmel DSP and about 45% compared with 7MS320c15x.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2007.06a
• /
• pp.754-757
• /
• 2007

In this paper, we present an implementation and it's real-sea test of an underwater acoustic data communication system, which allows the system to reduce complexity and increase robustness in time variant underwater environments. For easy adaptation to complicated and time-varying environments of the ocean, all-digital transmitter and receiver systems were implemented. For frame synchronization the CAZAC sequence was used, and QPSK modulation/ demodulation method with carrier frequency of 25kHz and a bandwidth of 5kHz were applied to generate 10kbps transmission rate including overhead. To improve transmission quality, we used several techniques and algorithms such as adaptive beamforming, adaptive equalizer, and convolution coding/Viterbi decoding. for the verification of the system performance, measurement of BER has been done in a very shallow water with depth of 8m at JangMok, Geoje. During the experiment, image data were successfully transmitted up to about 7.4km.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.6 s.336
• /
• pp.39-48
• /
• 2005

This paper proposes a reconfigurable coprocessor for communication systems, which can perform high speed computations and various functions. The proposed reconfigurable coprocessor can easily implement communication operations, such as scrambling, interleaving, convolutional encoding, Viterbi decoding, FFT, etc. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18$\mu$m standard cell library. The gate count is about 35,000 gates and the critical path is 3.84ns. The proposed coprocessor can reduced about $33\%$ for FFT operations and complex MAC, $37\%$ for Viterbi operations, and $48\%\~84\%$ for scrambling and convolutional encoding for the IEEE 802.11a WLAN standard compared with existing DSPs. The proposed coprocessor shows Performance improvements compared with existing DSP chips for communication algorithms.

• Journal of the Institute of Convergence Signal Processing
• /
• v.7 no.1
• /
• pp.17-23
• /
• 2006

In recent years, RFID has received much attention because of spread usage in industrial applications including factory, material flow, logistics and defense areas. However, there is only CRC-16 for error detection in ISO/IEC 18000-6 Protocols prepared for 860-960 MHz RFID, high error rates are expected in cases of high level of security and noisy envirionment. In this paper, we propose a usage of convolution code as a method for satisfying the high level of security requirement and system error performance.'1'he signal control function is implemented in a microprocessor with RF modulation and the convolutional encoding and Viterbi decoding are implemented in an FPGA chip.'The frame error rates are measured with and without convolution coding under the channel conditions of line-of- sight and non line-of-sight, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.11 no.4
• /
• pp.657-665
• /
• 2000

In this study, the bit error rate(BER) performance for the speech and data traffic is evaluated by results of the reverse link simulation of CDMA-based IMT-2000. Simulations in the reverse link are achieved for indoor, pedestrian, and vehicular environments, which are provided by ITU-R . Also, in the these simulations, the fast power control of 1.6kHz rate is applied. The amplitude and phase of the fading signal are estimated by using the 5-tap FIR filter, and the soft-decision Viterbi and Reed-Solomon (RS) decoding are applied. Simulation results provide the optimum ratio of pilot power to traffic power, the BER performance according to the number of fingers, and performance comparison between convolutional code and concatenated code at $10^-6$ BER in 5 MHz system.

• The Journal of Korean Institute of Information Technology
• /
• v.17 no.3
• /
• pp.31-41
• /
• 2019

In this paper, we design and implement the simulator for the transmitter and receiver of 4D-8PSK TCM with 2.0, 2.25, 2.5, and 2.75 bits/symbol-channel transmission efficiency recommended by the CCSDS for satellite communications, and then analyze the BER performance of 4D-8PSK TCM system in AWGN channel. The transmitter of 4D-8PSK TCM is designed in accordance with the recommendation in the CCSDS standard. Meanwhile, for the receiver design of 4D-8PSK TCM, we design the differential decoder generalizing the differential encoder/decoder scheme. The trellis decoding algorithm is designed by applying the auxiliary trellis information and the Viterbi algorithm, and an 8-dimensional constellation mapper equation given in the CCSDS standard is deconstructed to design constellation mapper. Especially, we present the optimized receiver for 4D-8PSK TCM system by investigating the BER performances for the traceback lengths in the Viterbi decoder through computer simulations..

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.16 no.2
• /
• pp.63-70
• /
• 2016

To increase throughput efficiency and improve performance, FTN(Faster Than Nyquist) method and LDPC(Low Density Parity Code) codes are employed in DVB-S3 system. In this paper, we proposed efficient turbo equalization model to minimize inter symbol interference induced by FTN transmission. This paper introduces two conventional scheme employing SIC(Successive Interference Cancellation) and BCJR equalizer. Then, we proposed new scheme to resolve problems in this two conventional scheme. To make performance improved in turbo equalization model, the outputs of LDPC and BCJR equalizer are iteratively exchange probabilistic information. In fed LDPC outputs as extrinsic informa tion of BCJR equalizer. we split LDPC output to separate bit probabilities. We compare performance of proposed scheme to that of conventional methods through using simulation in AWGN(Additive White Gaussian Noise) channel. We confirmed that performance was improved compared to conventional methods as increasing throughput parameters of FTN.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.11
• /
• pp.14-23
• /
• 2002

Two implementation methods for SOVA (Soft Output Viterbi Algorithm)of Turbo decoder are applied and verfied. The first method is the combination of a trace back (TB) logic for the survivor state and a double trace back logic for the weight value in two-step SOVA. This architecure of two-setp SOVA decoder allows important savings in area and high-speed processing compared with that of one-step SOVA decoding using register exchange (RE) or trace-back (TB) method. Second method is adjusting the reliability value with a scaling factor between 0.25 and 0.33 in order to compensate for the distortion for a rate 1/3 and 8-state SOVA decoder with a 256-bit frame size. The proposed schemes contributed to higher SNR performance by 2dB at the BER 10E-4 than that of SOVA decoder without a scaling factor. In order to verify the suggested schemes, the SOVA decoder is testd using Xillinx XCV 1000E FPGA, which runs at 33.6MHz of the maximum speed with 845 latencies and it features 175K gates in the case of 256-bit frame size.