• Title/Summary/Keyword: Video Signal Processing

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Thermal Imager Implementation Using Infrared Sensor (적외선 센서를 이용한 열상장비의 구현)

  • Yu, W.K.;Yoon, E.S.;Kim, C.W.;Song, I.S.;Hong, S.M.
    • Proceedings of the KIEE Conference
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    • 1992.07b
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    • pp.1250-1254
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    • 1992
  • This paper describes the designed and fabricated thermal imaging system with the SPRITE(Signal PRocessing in The Element) detector, operating in the 3-12 micron band. This system consists of an afocal telescope, a scan unit containing the SPRITE detector, an electronic processor unit and a cooler. The optical scan system utilizing rotating polygon and oscillating mirror, is 2-dimensional serial/parallel scan type using five elements of the detector. And the electronic processor unit performs digital scan conversion to reform the parallel data stream into serial analog data compatable with conventional RS-170 video. The scan field of view is 40 ${\times}$ 26.7 and the MRTD(Minium Resolvable Temperature Difference) is 0.6 K at 7.5 cycles/mm. The acquired thermal image indicates that this system has a satisfactory performance.

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Development of Obstacle Detection System on a Railroad Crossing (철도건널목 지장물 영상검지장치 개발)

  • Cho, Bong-Kwan;Ryu, Sang-Hwan
    • Proceedings of the KIEE Conference
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    • 2009.07a
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    • pp.1197_1198
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    • 2009
  • The development of Technology study for preventing of accident and reducing the risk through the intelligence of level crossing is provide the detection of stopped car at railway crossing with the most advanced intelligence technology such as sensor, computer, communication and date processing and transmit to the operational staff on broad for reaction or make the train stopped automatically through the connection with train. Also this study include that showing the situation of crossing railway when the train is approached and prevent the accident and reduce the risk through the connection of road transit signal system. On this study is performed the test through the date from spot level crossing and the development of video detection algorism for stopped road transit vehicle at level crossing with intelligent system.

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Design of Subband Image Encoder by Discrete Wavelet Transform

  • Huh, Young;Rhee, Kang-Hyeon
    • Proceedings of the IEEK Conference
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    • 2002.07b
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    • pp.864-867
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    • 2002
  • Introduction of digital communication network such as Integrated Services Digital Networks(ISDN) and digital storage media have rapidly developed. Due to a large amount of image data, compression is the key techniques in still image and video using digital signal processing for transmitting and storing. Digital image compression provides solutions for various image applications that represent digital image requiring a large amount of data. in this paper, the proposed DWT(Discrete Wavelet Transform) filter bank is consisted of simple architecture, but it is efficiently designed that a user obtains a wanted compression rate as only input parameter. If it is implemented by FPGA chip, the designed encoder operates in 12MHz.

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Novel Adaptive De-interlacing Algorithm using Temporal Correlation

  • Ku, Su-Il;Jung, Tae-Young;Jeong, Je-Chang
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2009.01a
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    • pp.199-202
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    • 2009
  • This paper proposes a novel adaptive algorithm for deinterlacing. In the proposed algorithm, the previously developed Enhanced ELA [6], Chen [9] and Li [10] algorithms were used as a basis. The fundamental mechanism was the selection and application of the appropriate algorithm according to the correlation with the previous and next field using temporal information. Extensive simulations were conducted for video sequences and showed good performance in terms of peak signal-to-ratio (PSNR) and subjective quality.

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An Image Segmentation Technique For Very Low Bit Rate Video Coding

  • Jung, Seok-Yoon;Kim, Rin-Chul;Lee, Sang-Uk
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 1997.06a
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    • pp.19-24
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    • 1997
  • This paper describes an image segmentation technique for the object-oriented coding at very low bit rates. By noting that, in the object-oriented coding technique, each objects are represented by 3 parameters, namely, shape, motion, and color informations, we propose a segmentation technique, in which the 3 parameters are fully exploited. To achieve this goal, starting with the color space conversion and the noise reduction, the input image is divided into many small regions by the K-menas algorithm on the O-K-S color space. Then, each regions are merged, according to the shape and motion information. In simultations, it is shown that the proposed technique segments the input image into relevant objects, according to the shape and motion as well as the colors. In addition, in order to evaluate the performance of the proposed technique, we introduce the notion of the interesting regions, and provide the results of encoding the image with emphasizing the interesting regions.

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Joint Optimization of Error Resilient Video Coding and Error Correction Coding Technique over Wireless Mobile Channels (이동통신 환경에서 전송 오류에 강인한 영상 부호화 기법과 오류 정정 부호화 기법의 동시 최적화에 관한 연구)

  • 이창우;김종원
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.26 no.6B
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    • pp.802-809
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    • 2001
  • 이동통신 채널에서 압축된 동영상 정보를 전송하게 되면 다경로 전송으로 인한 페이딩 영향과 시, 공간상으로 압축된 동영상 정보의 오류 전파 때문에 최종적으로 복원되는 동영상 신호의 화질이 크게 저하된다. 이에 능동적으로 대처하기 위하여 다양한 오류 정정 부호화 기법들이 전체 정보량 증가를 감수하면서 제안되어 왔다. 본 논문에서는 이동통신 환경에서 압축된 동영상 신호의 안정적인 전송을 위해서 ITU-T H.263 기법으로 압축된 동영상 정보에 두 종류의 다전송율 지원 오류 정정 부호들을 적용한 경우의 동영상 보호 능력을 분석 비교한다. 즉 표준기법에서 널리 사용되는 RCPC(rate compatible punctured convolutional) 부호와 RC 특성을 갖는 turbo 부호인 RCPT(rate compatible punctured turbo) 부호를 사용한 동영상 부호 시스템의 성능을 가산 백색 잡음 채널과 레일리 페이딩 채널에서 해석하고, 압축과 오류 정정 부호화율의 동시 최적화를 살펴본다.

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Implementation of 2-D DCT/IDCT VLSI based on Fully Bit-Serial Architecture (완전 비트 순차 구조에 근거한 2차원 DCT/IDCT VLSI 구현)

  • 임호근;류근장;권용무;김형곤
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.6
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    • pp.188-198
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    • 1994
  • The distributed arithmetic approach has been commonly recognized as an efficient method to implement the inner-product type of computation with fixed coefficients such as DCT/IDCT. This paper presents a novel architecture and the implementation of 2-D DCT/IDCT VLSI chip based on distributed arithmetic. The main feature of the proposed architecture is a fully 2-bit serial pipeline and parallel structure with memory-based signal processing circuitry, which is efficient to the implementation of the bit-serial operation of distributed arithmetic. All modules of the proposed architecture are designed with NP-dynamic circuitry to reduce the power consumption and to increase the performance. This chip is applicable in HDTV systems working at video sampling rate up to 75 MHz.

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A Study on Adaptive Information Hiding Technique for Copyright Protection of Digital Images (디지털 영상물의 저작권 보호를 위한 적응적 정보 은닉 기술에 관한 연구)

  • Park, Kang-Seo;Chung, Tae-Yun;Oh, Sang-Rok;Park, Sang-Hee
    • Proceedings of the KIEE Conference
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    • 1998.07g
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    • pp.2427-2429
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    • 1998
  • Digital watermarking is the techinque which embeds the invisible signal into multimedia data such as audio, video, images, for copyright protection, including owner identification and copy control information. This paper proposes a new watermark embedding and extraction technique by extending the direct sequence spread spectrum technique. The proposed technique approximates the frequency component of pixels in spatial domain by using Laplacian mask and adaptively embeds the watermark considering the HVS to reduce the degradation of Image. In watermark extraction process, the proposed technique strengthens the high frequency components of image and extracts the watermark by demodulation. All this processes are performed in spatial domain to reduce the processing time.

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Direct Sequence Spread Spectrum Transmitter using FPGAs

  • Abhijit S. Pandya;Souza, Ralph-D′;Chae, Gyoo-Yong
    • Journal of information and communication convergence engineering
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    • v.2 no.2
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    • pp.76-79
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    • 2004
  • The DS-SS (Direct Sequence Spread Spec1nun) transmitter is part of a low data rate (∼150 kbps - burst rate and 64 bps - average data rate) wireless communication system. It is traditionally implemented using Digital Signal processing chip (DSP). However, with rapid increase in variety of services through cell phones, such as, web access, video transfer, online games etc. demand for higher rate is increasing steadily. Since the chip rate and thereby the sampling rate requirements of the system are fairly high, the transmitter should implemented using Field programmable Gate Arrays FPGAs instead of a DSP. This paper shows the steps taken to get a working prototype of the transmitter unit on a FPGA based platform.

ON RECORD/PLAYBACK SIGNAL PROCESSING METHOD FOR DVCR WITH HIGHER AREAL DENSITY

  • Lee, Sang-Moon;Park, Young-Joon;Sheen, Yong-Hoo;Kim, Yung-Gil
    • Journal of the Korean Magnetics Society
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    • v.5 no.5
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    • pp.650-654
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    • 1995
  • In digital video recording, higher areal density is strongly required for realizing digital VCRs. In order to accomplish higher areal density. we have implemented a system that has a narrow track pitch and can record data of about 30 Mbps(15 Mbps per channel) with the conventional S-VHS tapes. After computer simulation using the characteristics of the experimental system, we have selected appropriate equalizer and detection method by taking into account performance and cost (including hardware complexity). As a result, the selected equalizer and detection schemes are cosine equalizer and integrated de tection, respectively. The implemented system confirms reliable operation with a symbol error rate of less than $1{\times}10^{-4}$. In this paper, We will show the performance of the implemented system together with simulation results.

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