• Journal of The Korean Association For Science Education
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• v.38 no.2
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• pp.273-291
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• 2018

Gestures accompanied by scientific discourses play an important role in constructing mental models and making model-based inferences. According to embodied cognition literature, gestures can be a source of recognition of the mental models of students and help them in changing naive beliefs about science. This study intends to compare the gestures of scientists with that of middle school students in explaining scientific phenomena and to explore the relationship between gestures and scientific discourse. In the study, 10 scientists and 10 middle school students participated in clinical interviews and the tests of knowledge and self-efficacy. Participants engaged in one-on-one clinical interviews with semi-structured questions about three tasks regarding the molecular movement and the state change of matter. Four researchers carried out open coding and applied a constant comparison method in order to analyze video-recorded gestures. This study found four themes (feature of gesture, use of gesture, content of gesture, function of gesture) about the differences of gestures between scientists and middle school students. Scientists used more diverse and elaborate gestures systematically and frequently in the interview. Although students used gestures in their scientific talk and reasoning, the gestures of students were not well grounded on scientific knowledge and had different functions from those of scientists. The findings revealed that gestures can represent underlying cognition and strengthen scientific thinking. We should encourage students to use gestures as a tool to understand scientific concepts and make inferences.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.50-57
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• 2009

This paper proposes a VLSI architecture of CAVLC hardware decoder which is a tool eliminating statistical redundancy in H.264/AVC video compression. The previous CAVLC hardware decoder used four stages to decode five code symbols. The previous CAVLC hardware architectures decreased decoding performance because there was an unnecessary idle cycle in between state transitions. Likewise, the computation of valid bit length includes an unnecessary idle cycle. This paper proposes hardware architecture to eliminate the idle cycle efficiently. Two methods are applied to the architecture. One is a method which eliminates an unnecessary things of buffers storing decoded codes and then makes efficient pipeline architecture. The other one is a shifter control to simplify operations and controls in the process of calculating valid bit length. The experimental result shows that the proposed architecture needs only 89 cycle in average for one macroblock decoding. This architecture improves the performance by about 29% than previous designs. The synthesis result shows that the design achieves the maximum operating frequency at 140Mhz and the hardware cost is about 11.5K under a 0.18um CMOS process. Comparing with the previous design, it can achieve low-power operation because this design is implemented with high throughputs and low gate count.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.1
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• pp.35-41
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• 2000

This paper considers the consturction of 24/25 I-NRZI (Interleaved - Non Return to Zero Inverse) modulator designs for DVCR (Digital Video Cassette Recorder), and size of validity bit in order to store the amplitude value of square-wave and the standard data ( sine and cosine coefficients) at ROM Table that to acceptable the spectrum standard. The validity bit size of the standard data and the amplitude value of square-wave that to store at ROM Table are affected the size of pilot signal on the output spectrum, and the hardware size of modulator. At the designable 24/25 I-NRZI modulator, we simulated using random pattern (F0,F1,F2) that to verification the output data of the spectrum. Moreover, the resultant of the spectrum analysis, at the optimizing value, is 0.065 on the amplitude value of square-wave, and 3bit on the size of bit in order to store the standared data at ROM Table. In order to verify the hardware of designable 24/25 I-NRZI modulator, we perform to modeling of C-language firstly, and coding to Verilog HDL (Cadence Verilog XL) and synthesized using Synopsys (Library "Samsung KG75") tool as a base of spectrum results. In a foundation of this result, we are considered the size of hardware. In this paper, a considerable 24/25 I-NRZI modulator designable less than 10,000 gates as that is improved consturction as regards the path method of pre-coder etc, and able to application digital camcorders as now practical use.