• 대한금속재료학회지
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• 제48권11호
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• pp.1028-1034
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• 2010

In the development of 3D package, through silicon via (TSV) formation technology by using deep reactive ion etching (DRIE) is one of the key processes. We performed the Bosch process, which consists of sequentially alternating the etch and passivation steps using $SF_6$ with $O_2$ and $C_4F_8$ plasma, respectively. We investigated the effect of changing variables on vias: the gas flow time, the ratio of $O_2$ gas, source and bias power, and process time. Each parameter plays a critical role in obtaining a specified via profile. Analysis of via profiles shows that the gas flow time is the most critical process parameter. A high source power accelerated more etchant species fluorine ions toward the silicon wafer and improved their directionality. With $O_2$ gas addition, there is an optimized condition to form the desired vertical interconnection. Overall, the etching rate decreased when the process time was longer.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.418-418
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• 2008

The electrochemical etching of silicon in HF-based solutions is known to form various types of porous structures. Porous structures are generally classified into three categories according to pore sizes: micropore (below 2 nm in size), mesopore (2 ~ 50 nm), and macropore (above 50 nm). Recently, the formation of macropores has attracted increasing interest because of their promising characteristics for an wide scope of applications such as microelectromechanical systems (MEMS), chemical sensors, biotechnology, photonic crystals, and photovoltaic application. One of the promising applications of macropores is in the field of MEMS. Anisotropic etching is essential step for fabrication of MEMS. Conventional wet etching has advantages such as low processing cost and high throughput, but it is unsuitable to fabricate high-aspect-ratio structures with vertical sidewalls due to its inherent etching characteristics along certain crystal orientations. Reactive ion dry etching is another technique of anisotropic etching. This has excellent ability to fabricate high-aspect-ratio structures with vertical sidewalls and high accuracy. However, its high processing cost is one of the bottlenecks for widely successful commercialization of MEMS. In contrast, by using electrochemical etching method together with pre-patterning by lithographic step, regular macropore arrays with very high-aspect-ratio up to 250 can be obtained. The formed macropores have very smooth surface and side, unlike deep reactive ion etching where surfaces are damaged and wavy. Especially, to make vertical microwire or nanowire arrays (aspect ratio = over 1:100) on silicon wafer with top-down photolithography, it is very difficult to fabricate them with conventional dry etching. The electrochemical etching is the most proper candidate to do it. The pillar structures are demonstrated for n-type silicon and the formation mechanism is well explained, while such a experimental results are few for p-type silicon. In this report, In order to understand the roles played by the kinds of etching solution and mask patterns in the formation of microwire arrays, we have undertaken a systematic study of the solvent effects in mixtures of HF, dimethyl sulfoxide (DMSO), iso-propanol, and mixtures of HF with water on the structure formation on monocrystalline p-type silicon with a resistivity with 10 ~ 20 $\Omega{\cdot}cm$. The different morphological results are presented according to mask patterns and etching solutions.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.454-454
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• 2014

Silicon microwire array is one of the promising platforms as a means for developing highly efficient solar cells thanks to the enhanced light trapping efficiency. Among the various fabrication methods of microstructures, deep reactive ion etching (DRIE) process has been extensively used in fabrication of high aspect ratio microwire arrays. In this presentation, we show precisely controlled Si microwire arrays by tuning the DRIE process conditions. A periodic microdisk arrays were patterned on 4-inch Si wafer (p-type, $1{\sim}10{\Omega}cm$) using photolithography. After developing the pattern, 150-nm-thick Al was deposited and lifted-off to leave Al microdisk arrays on the starting Si wafer. Periodic Al microdisk arrays (diameter of $2{\mu}m$ and periodic distance of $2{\mu}m$) were used as an etch mask. A DRIE process (Tegal 200) is used for anisotropic deep silicon etching at room temperature. During the process, $SF_6$ and $C_4F_8$ gases were used for the etching and surface passivation, respectively. The length and shape of microwire arrays were controlled by etching time and $SF_6/C_4F_8$ ratio. By adjusting $SF_6/C_4F_8$ gas ratio, the shape of Si microwire can be controlled, resulting in the formation of tapered or vertical microwires. After DRIE process, the residual polymer and etching damage on the surface of the microwires were removed using piranha solution ($H_2SO_4:H_2O_2=4:1$) followed by thermal oxidation ($900^{\circ}C$, 40 min). The oxide layer formed through the thermal oxidation was etched by diluted hydrofluoric acid (1 wt% HF). The surface morphology of a Si microwire arrays was characterized by field-emission scanning electron microscopy (FE-SEM, Hitachi S-4800). Optical reflection measurements were performed over 300~1100 nm wavelengths using a UV-Vis/NIR spectrophotometer (Cary 5000, Agilent) in which a 60 mm integrating sphere (Labsphere) is equipped to account for total light (diffuse and specular) reflected from the samples. The total reflection by the microwire arrays sample was reduced from 20 % to 10 % of the incident light over the visible region when the length of the microwire was increased from $10{\mu}m$ to $30{\mu}m$.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 추계학술발표대회
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• pp.17.2-17.2
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• 2011

Double-walled carbon nanotubes (DWCNTs) were grown with vertical alignment on a Si wafer by using catalytic thermal chemical vapor deposition. This study investigated the effect of pre-annealing time of catalyst on the types of CNTs grown on the substrate. The catalyst layer is usually evolved into discretely distributed nanoparticles during the annealing and initial growth of CNTs. The 0.5-nm-thick Fe served as a catalyst, underneath which Al was coated as a catalyst support as well as a diffusion barrier on the Si substrate. Both the catalyst and support layers were coated by using thermal evaporation. CNTs were synthesized for 10 min by flowing 60 sccm of Ar and 60 sccm of H2 as a carrier gas and 20 sccm of C2H2 as a feedstock at 95 torr and $750^{\circ}C$. In this study, the catalyst and support layers were subject to annealing for 0~420 sec. As-grown CNTs were characterized by using field emission scanning electron microscopy, high resolution transmission electron microscopy, Raman spectroscopy, and atomic force microscopy. The annealing for 90~300 sec caused the growth of DWCNTs as high as ~670 ${\mu}m$ for 10 min while below 90 sec and over 420 sec 300~830 ${\mu}m$-thick triple and multiwalled CNTs occurred, respectively. Several radial breathing mode (RBM) peaks in the Raman spectra were observed at the Raman shifts of 112~191 cm-1, implying the presence of DWCNTs, TWCNTs, MWCNTs with the tube diameters 3.4, 4.0, 6.5 nm, respectively. The maximum ratio of DWCNTs was observed to be ~85% at the annealing time of 180 sec. The Raman spectra of the as-grown DWCNTs showed low G/D peak intensity ratios, indicating their low defect concentrations. As increasing the annealing time, the catalyst layer seemed to be granulated, and then grown to particles with larger sizes but fewer numbers by Ostwald ripening.

• 한국전기전자재료학회논문지
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• 제26권4호
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• pp.271-274
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• 2013

Power Metal Oxide Semiconductor Field Effect Transistor's (MOSFETs) are well known for superior switching speed, and they require very little gate drive power because of the insulated gate. In these respects, power MOSFETs approach the characteristics of an "ideal switch". The main drawback is on-resistance RDS(on) and its strong positive temperature coefficient. While this process has been driven by market place competition with operating parameters determined by products, manufacturing technology innovations that have not necessarily followed such a consistent path have enabled it. This treatise briefly examines metal oxide semiconductor (MOS) device characteristics and elucidates important future issues which semiconductor technologists face as they attempt to continue the rate of progress to the identified terminus of the technology shrink path in about 2020. We could find at the electrical property as variation p base dose. Ultimately, its ON state voltage drop was enhanced also shrink chip size. To obtain an optimized parameter and design, we have simulated over 500 V Field ring using 8 Field rings. Field ring width was $3{\mu}m$ and P base dose was $1e15cm^2$. Also the numerical multiple $2.52cm^2$ was obtained which indicates the doping limit of the original device. We have simulated diffusion condition was split from $1,150^{\circ}C$ to $1,200^{\circ}C$. And then $1,150^{\circ}C$ diffusion time was best condition for break down voltage.

• 한국생산제조학회지
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• 제22권6호
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• pp.996-1002
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• 2013

This study addresses the development of a full duplex robotic system for transferring flat-panel display glass. We propose to accomplish this using a bidirectional linear transfer mechanism in place of the conventional rotary transfer mechanism. The developed full duplex robot comprises a driving part that carries the glass panel laterally, vertical part that can be moved up and down by means of a ball screw and linear motion guide arrangement, and hand part that slides by the cylinder of the driving part along the guide rail with a V-guide bearing attached to the bottom of the support. In addition, an alignment part prevents the hand part from derailing and holds the hand part while the driving part moves horizontally. The full duplex robot lifts and drives a glass panel directly while transferring it to the buffer and does not require rotational motion. Therefore, both transferring and stacking are realized with a single device. This device can be used in existing industrial facilities as an alternative to existing industrial robots in current as well as future process lines. The proposed full duplex robot is expected to save considerable amounts of time and space, and increase product throughput.

• 마이크로전자및패키징학회지
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• 제8권4호
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• pp.17-23
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• 2001

3차원 홀 센서는 두 개의 수평 자계($\chi$, y성분) 검출부와 한 개의 수직 자계(z 성분) 검출부를 갖는다. 종래의 3차원 홀 센서는 일반적으로 $B_{z}$에 대한 감도가 $B_\chi, B_y$에 대한 감도의 약 1/10정도에 그친다. 본 연구에서는 새로운 구조를 갖는 3차원 홀 센서를 제안하였다. 이방성 식각을 이용하여 트랜치를 형성함으로써 감도를 약 6배 증가시켰다. 또한 자속을 집속시키기 위하여 웨이퍼 후면에 강자성체 박막을 증가시킴으로써 $B_{z}$에 대한 감도를 $B_\chi, B_y$에 대한 감도의 약 80% 정도로 증가시켰다. 전류 3 mA를 인가했을 때, Ni/Fe 박막을 증착하여 제작된 센서의 감도는 $B_\chi, B_y$, B$_{z}$ 에 대하여 각각 120.1 mV/T, 111.7 mV/T, 그리고 95.3 mV/T로 측정되었다. 센서의 선형성을 오차가 $\pm$3%로 우수하였다.

• 마이크로전자및패키징학회지
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• 제13권4호
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• pp.45-50
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• 2006

3D package의 SiP에서 구리의 via filling은 매우 중요한 사항으로 package밀도가 높아짐에 따라 via의 크기가 줄어들며 전기도금법을 이용한 via filling이 연구되어왔다. Via filling시 via 내부에 결함이 발생하기 쉬운데 전해액 내에 억제제, 가속제등 첨가제를 첨가하고 펄스-역펄스(PRC)의 전류파형을 인가하여 결함이 없는 via의 filling이 가능하다. 본 연구에서는 건식 식각 방법 중 하나인 DRIE법을 이용하여 깊이 $100{\sim}190\;{\mu}m$, 직경이 각각 $50{\mu}m,\;20{\mu}m$인 2가지 형태의 via을 형성하였다. DRIE로 via가 형성된 Si wafer위에 IMP System으로 Cu의 Si으로 확산을 막기 위한 Ta층과 전해도금의 씨앗층인 Cu층을 형성하였다. Via시편은 직류, 펄스-역펄스의 전류 파형과 억제제, 가속제, 억제제의 첨가제를 모두 사용하여 filling을 시도하였고, 공정 후 via의 단면을 경면 가공하여 SEM으로 관찰하였다.

• 한국정보통신학회논문지
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• 제3권3호
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• pp.661-669
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• 1999

프로브 카드는 IC(integrated circuit) 칩을 테스트할 때, 테스트 시스템의 가장 중요한 부분의 하나이다. 본 연구는 다수의 반도체 칩을 동시에 테스트 할 수 있는 범프(bump)형 수직형 프로브 카드에 관한 것이다. 프로브는 범프 팁을 가지는 실리콘 캔틸레버로 구성되어 있다. 캔틸레버의 최적 크기를 결정하기 위하여 캔틸레버의 크기는 유한요소해석에 의하여 결정되었다. 프로브는 SDB웨이퍼를 사용하여 RIE, 등방성 에칭, 그리고 벌크 마이크로머시닝에 의하여 제조되었다. FEM에 의해 결정된 최적 크기로 제작된 프로브 카드는 범프의 높이가 30$\mum$, 캔틸레버의 두께가 $\mum$, 빔의 폭이 100 $\mum$, 길이가 400 $\mum$, 이었다. 제조된 프로브 카드의 접촉 테스트에서 측정된 접촉 저항은 $2 \Omega$ 미만이고, 2만회의 접촉동안 접촉 저항의 변화가 거의 없는 특성을 보였다. 따라서 20,000회 이상의 수명을 가질 수 있음을 알 수 있었다.

• Applied Science and Convergence Technology
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• 제26권4호
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• pp.79-85
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• 2017

The crack-free AlGaN template has been successfully grown by using selective area growth with triangular GaN facet. The triangular GaN stripe structure was obtained by vertical growth rate enhanced mode with low growth temperature of $950^{\circ}C$ and high growth pressure of 500 torr. The lateral growth rate enhanced mode of AlGaN for crack-free and flat surface was also investigated. Low pressure of 30 torr and high V/III ratio of 4400 were favorable for lateral growth of AlGaN. It was confirmed that the $4{\mu}m$ -thick $Al_{0.2}Ga_{0.8}N$ was crack-free over entire 2-inch wafer. The dislocation density of $Al_{0.2}Ga_{0.8}N$ was as low as ${\sim}7.6{\times}10^8/cm^2$ measured by cathodoluminescence. Based on the high quality AlGaN with low dislocation density, the ultraviolet laser diode epitaxy with cladding, waveguide and GaN/AlGaN multiple quantum well (MQW) was grown by metalorganic chemical vapor deposition. The stimulated emission at 349 nm with full width at half maximum of 1.8 nm from the MQW was observed through optical pumping experiment with 193 nm KrF laser. We also have fabricated the deep ridge type ultraviolet laser diode (UV-LD) with $5{\mu}m-wide$ and $700{\mu}m-long$ cavity for electrical properties. The turn on voltage was below 5 V and the resistance was ${\sim}55{\Omega}$ at applied voltage of 10 V. The amplified spontaneous emission spectrum of UV-LD was also observed from pulsed current injection.