• ETRI Journal
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• v.11 no.4
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• pp.22-36
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• 1989

In this paper, a design and implementation of an efficient protocol verification system named LOVE has been described. The LOVE has been developed specifically for LOTOS. It performs not only protocol syntax validation (PSV) but also protocol functional verification(PFV). The PSV is a test to check if a protocol is free from protocol syntax errors such as deadlocks and livelocks. The PFV confirms whether or not a protocol achieves its functional objectives. For the PSV, the reachability analysis is employed, and the observational equivalence test is used for the PFV. For protocol verification using the LOVE, a schematic protocol verification methodology has been outlined.

• Journal of the Korean Society for Railway
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• v.7 no.2
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• pp.114-119
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• 2004

According to the computerization of railway signalling systems. the communication protocol for interface between these systems are required. Therefore the new communication protocol for railway signaling system is required. Generally, there are two verification method for new designed protocol in the industrial and academic fields. One is the laboratory testing method which is very popular and general technique. In our research the comparison between existing and new designed protocol for signaling is described and the verification test results are also represented. From these laboratory test, we are verified the conformance of new designed protocol. Another method is verified by formal method. The format verification method is widely used at safety-critical system design but this approach is nor popular at verification communication protocol. However it is very important to verify the safety of new designed protocol for railway signaling system because signaling systems are very safety-critical systems. So, the methodology for formal verification of designed protocol is also reviews in this paper.

• Journal of Electrical Engineering and Technology
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• v.1 no.4
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• pp.513-519
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• 2006

As a very important part in development of the protocol, verifications for developed protocol specification are complementary techniques that are used to increase the level of confidence in the system functions by their specifications. Using the informal method for specifying the protocol, some ambiguity may be contained therein. This indwelling ambiguity in control systems can cause the occurrence of accidents, especially in the case of safety-critical systems. To clear the vagueness contained in the designed protocol, we use the LTS (Labeled Transition System) model to design the protocol for railway signaling. And then, we verify the safety and the liveness properties formally through the model checking method. The modal ${\mu}$-calculus, which is an expressive method of temporal logic, has been applied to the model checking method. We verify the safety and liveness properties of Korean standard protocol for railway signaling systems. To perform automatic verification of the safety and liveness properties of the designed protocol, a communication verification tool is implemented. The developed tools are implemented by C++ language under Windows XP. It is expected to increase the safety and reliability of communication protocol for signaling systems by using the developed communication verification tool.

• Korean Journal of Adult Nursing
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• v.20 no.2
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• pp.353-363
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• 2008

Purpose: This study was conducted to develop a timeout protocol as the process of patients verification in the operating room, and to evaluate its effects. Methods: The timeout protocol was developed based on the experience of practices and the universal protocol of JCAHO 2004. The subjects of this study were 192 surgical members working in the operating room at an university hospital in Daegu, Korea. Results: The timeout protocol was developed in six steps; participants verification, encouragement of compliance, verification of right 3 PSP, agreement of surgical team members, verification of the parties to a patient, patient agreement. The data which have been resulted from the experimental group show significantly higher than those of control group as follows; cognition(t = -6.580, p = .000), contents of performance; progress of anesthesiologist as leader(${\chi}^2$ = 29.029, p = .000), verification of right patient, right site and right procedure(${\chi}^2$ = 40.663, p = .000), participation of surgical team(${\chi}^2$ = 68.412, p = .000), and the number of cases of performance(${\chi}^2$ = 242.900, p = .000). Conclusion: It suggests that medical accidents caused by failures in a preoperative verification process can be prevented if a timeout is conducted active involvement and effective communication among surgical team members for a final verification of the correct patient, procedure, and site.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.10
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• pp.4703-4723
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• 2016

The verification of data integrity is an urgent topic in remote data storage environments with the wide deployment of cloud data storage services. Many traditional verification algorithms focus on the block-oriented verification to resolve the dispute of dynamic data integrity between the data owners and the storage service providers. However, these algorithms scarcely pay attention to the data verification charge and the users' verification experience. The users more concern about the availability of accessed files rather than data blocks. Moreover, the data verification charge limits the number of checked data in each verification. Therefore, we propose a mixed verification protocol to verify the data integrity, which rapidly locates the corrupted files by the file-oriented verification, and then identifies the corrupted blocks in these files by the block-oriented verification. Theoretical analysis and simulation results demonstrate that the protocol reduces the cost of the metadata computation and transmission relative to the traditional block-oriented verification at the expense of little cost of additional file-oriented metadata computation and storage at the data owner. Both the opportunity of data extracted and the scope of suspicious data are optimized to improve the verification efficiency under the same verification cost.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.132-140
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• 2002

This paper presents an ARM-based SOC bus transaction verification IP and the usage experiences in SOC designs. The verification IP is an AMBA AHB protocol checker, which captures legal AHB transactions in FSM-style signal sequence checking routines. This checker can be considered as a reusable verification IP since it does not change unless the bus protocol changes. Our AHB protocol checker is designed to be scalable to any number of AHB masters and reusable for various AMBA-based SOC designs. The keys to the scalability and the reusability are Object-Oriented Programming (OOP), virtual port, and bind operation. This paper describes how OOP, virtual port, and bind features are used to implement AHB protocol checker. Using the AHB protocol checker, an AHB simulation monitor is constructed. The monitor checks the legal bus arbitration and detects the first cycle of an AHB transaction. Then it calls AHB protocol checker to check the expected AHB signal sequences. We integrate the AHB bus monitor into Verilog simulation environment to replace time-consuming visual waveform inspection, and it allows us to find design bugs quickly. This paper also discusses AMBA AHB bus transaction coverage metrics and AHB transaction coverage analysis. Test programs for five AHB masters of an SOC, four channel DMAs and a host interface unit are executed and transaction coverage for DMA verification is collected during simulation. These coverage results can be used to determine the weak point of test programs in terms of the number of bus transactions occurred and guide to improve the quality of the test programs. Also, the coverage results can be used to obtain bus utilization statistics since the bus cycles occupied by each AHB master can be obtained.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.358-362
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• 2004

Verification and testing are complementary techniques that are used to increase the level of confidence in the correct functioning of communication systems as prescribed by their specifications. This paper presents an experience of model checking for a formal railway signaling protocol specified in LTS (Labeled Transition System). This formal approach checks deadlock, livelock and reachability for the state and action to verify whether properties expressed in modal logic are true on specifications. We also propose a formal method for semi-automated test case generation for a railway signaling protocol described in I/O FSM (Input/Output Finite State Machine). This enables the generation of more complete and consistent test sequence for conformance testing. The above functions are implemented by C++ language and included within RSPVTE (Railway Signaling Protocol Verification and Testing Environment).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.96-104
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• 2006

This paper presents design methodology, encient verification and implementation of a CAN protocol controller. The design methodology uses a heuristic technique to make the design flexible and cost effective. Using the design methodology, we created architecture for a CAN controller which has flexible and low cost features. For faster time-to-market and reliable operation of the designed CAN protocol controller, we p개posed a three-step verification process which uses three different kinds of verification techniques. The goal of this three-step verification is to reduce the number of test sequences in order to rapidly implement the design without loss of reliability for faster time-to-market. The designed CAN protocol controller was fabricated using a 0.35 micrometer CMOS technology.

• Proceedings of the KSR Conference
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• 2004.10a
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• pp.1241-1246
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• 2004

The verification confirms a correspondence between requirements and a specification before implementing. The problem in the formal method verifying a protocol specification using model checking is that the protocol behaviors must be always specified in L TS(Label Transition System). But if Region Automata is applied to the model checking, it is enable to verify whether properties are true on specification specified in I/O FSM(Input/Output Finite State Machine) as well as LTS. In this paper, we verify the correctness of rail signal control protocol type 1 specified in I/O FSM by using model checking method and region automata. This removes many errors and ambiguities of an informal method used in the past and saves down expenditures and times required in the protocol development. Therefore it is expected that there will be an increase in safety, reliability and efficiency in terms of the maintenance of the signaling system by using the proposed verification methods.

• Journal of Electrical Engineering and information Science
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• v.1 no.1
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• pp.82-90
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• 1996

In this paper, we present an analysis of the IS-95 authentication protocol for the Code Division Multiple Access(CDMA) mobile communication network. We propose a mutual authentication protocol, AP-6, to improve the security and correctness. Formal description and verification of the proposed AP-6 are also presented on the basis of the formal logic. It is shown that the proposed AP-6 is more secure and correct than the IS-95 authentication protocol.