• Geomechanics and Engineering
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• v.32 no.3
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• pp.271-291
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• 2023

Settlement estimation in cohesion materials is a crucial topic to tackle because of the complexity of the cohesion soil texture, which could be solved roughly by substituted solutions. The goal of this research was to implement recently developed machine learning features as effective methods to predict settlement (S_m) of shallow foundations over cohesion soil properties. These models include hybridized support vector regression (SVR), random forests (RF), and coot optimization algorithm (COM), and black widow optimization algorithm (BWOA). The results indicate that all created systems accurately simulated the S_m, with an R² of better than 0.979 and 0.9765 for the train and test data phases, respectively. This indicates extraordinary efficiency and a good correlation between the experimental and simulated S_m. The model's results outperformed those of ANFIS - PSO, and COM - RF findings were much outstanding to those of the literature. By analyzing established designs utilizing different analysis aspects, such as various error criteria, Taylor diagrams, uncertainty analyses, and error distribution, it was feasible to arrive at the final result that the recommended COM - RF was the outperformed approach in the forecasting process of S_m of shallow foundation, while other techniques were also reliable.

• The KIPS Transactions:PartA
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• v.12A no.3 s.93
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• pp.263-272
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• 2005

The addressing mode for data is performed by the software in yon Neumann-concept(SISD) computer a priori without hardware design of an address counter for operands. Therefore, in the addressing mode for the vector the corresponding variables as much as the number of the elements should be specified and used also in the software method. This is because not for operand but only for an instructions, quasi PC(program counter) is designed in hardware physically. A vector has a characteristic of a structural dimension. In this paper we propose to design a hardware unit physically external to the CPU for addressing only the elements of a vector unit with the structure and dimension. Because of the high speed performance for a vector processing it should be designed in the SIMD pipeline mechanics. The proposed mechanics is evaluated through a simulation. Our result shows $12\%$ to $30\%$ performance enhancement over CRAY architecture under the same hardware consideration(processing unit).

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.201-208
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• 2014

In this paper, we propose the classifier structure design algorithm using DTW. Proposed algorithm uses DTW result to design the binary tree architecture based on the SVM which classify the multi-class data. Design the binary tree architecture for Support Vector Machine(SVM-BTA) using the threshold criterion calculated by the sum columns in square matrix which components are the reference data from each class. For comparison the performance of the proposed algorithm, compare the results of classifiers which binary tree structure are designed based on database and k-means algorithm. The data used for classification is 333 signals from 18 classes of underwater transient noise. The proposed classifier has been improved classification performance compared with classifier designed by database system, and probability of detection for non-biological transient signal has improved compare with classifiers using k-means algorithm. The proposed SVM-BTA classified 68.77% of biological sound(BO), 92.86% chain(CHAN) the mechanical sound, and 100% of the 6 kinds of the other classes.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.11b
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• pp.1229-1232
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• 2003

Ad Hoc 네트워크에서 on demand 라우팅 프로토콜로 대표적인 AODV(Ad Hoc On Demand Distance Vector Routing)는 table driven 기반의 라우팅 프로토콜과 비교해 active route만을 라우팅 테이블에 저장하기 때문에 오버헤드가 작고 경로단절시 경로복구를 통해 경로 재설정할 수 있는 장점을 가지고 있으나 경로복구시 대역폭 낭비가 심하고 복구시간이 길다는 drawback을 가지고 있다. 이러한 단점은 많은 라우팅 패킷의 발생으로 기인하는 점이 있다. 본 논문에서는 Expanding Ring Search 알고리즘에서 time out은 timestamp를 이용하여 네트워크 상황에 맞게 가변적으로 적용하는 알고리즘을 개선하여 hop 수에 따라 node traversal time을 설정하도록 제안하였다. 제안한 알고리즘은 시뮬레이션을 통하여 검증하였으며 라우팅 패킷의 발생을 줄이고 throughput에서 향상을 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.14-23
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• 2011

In this paper, a 7-bit 2GSPS folding/interpolation A/D Converter(ADC) with a Self-Calibrated Vector Generator is proposed. The ADC structure is based on a folding/interpolation architecture whose folding/interpolation rate is 4 and 8, respectively. A cascaded preprocessing block is not only used in order to drive the high input signal frequency, but the resistive interpolation is also used to reduce the power consumption. Based on a novel self-calibrated vector generator, further, offset errors due to device mismatch, parasitic resistors. and parasitic capacitance can be reduced. The chip has been fabricated with a 1.2V 0.13um 1-poly 7-metal CMOS technology. The effective chip area including the calibration circuit is 2.5$mm^2$. SNDR is about 39.49dB when the input frequency is 9MHz at 2GHz sampling frequency. The SNDR is improved by 3dB with the calibration circuit.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.124-129
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• 2013

This paper proposes a high-performance vector inner product calculation circuit for real-time object recognition based on SVM algorithm. SVM algorithm shows a higher detection rate than other object recognition algorithms. However, it requires a huge amount of computational efforts. Since vector inner product calculation is one of the major operations of SVM algorithm, it is important to implement a high-performance vector inner product calculation circuit for real-time object recognition capability. The proposed circuit adopts the pipeline architecture with six stages to increase the operating speed and makes it possible to recognize objects in real time based on SVM. The proposed circuit was described in Verilog HDL at RTL. For silicon verification, an MPW chip was fabricated using TSMC 180nm standard cell library. The operation of the implemented MPW chip was verified on the test board with test application software developed for the chip verification.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.159-161
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• 2017

In this paper, we propose an adaptive search range allocation algorithm for high-performance HEVC encoder and a hardware architecture suitable for the proposed algorithm. In order to improve the prediction performance, the existing motion vector is configured with the motion vectors of the neighboring blocks as prediction vector candidates, and a search range of a predetermined size is allocated using one motion vector having a minimum difference from the current motion vector. The proposed algorithm reduces the computation time by reducing the size of the search range by assigning the size of the search range to the rectangle and octagon type according to the structure of the motion vectors for the surrounding four blocks. Moreover, by using all four motion vectors, it is possible to predict more precisely. By realizing it in a form suitable for hardware, hardware area and computation time are effectively reduced.

• Journal of IKEEE
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• v.18 no.3
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• pp.305-312
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• 2014

IIt takes a lot of time and needs the workloads to verify the RTL code used in complex system like a nuclear control system which is required high level reliability using simple testbench. UVM has a layered testbench architecture and it is easy to modify the testbench to improve the code coverage. A test vector can be easily constructed in the UVM, since a constrained random test vector can be used even though the construction of testbench using UVM. We showed that the UVM testbench is easier than the verilog testbench for the analysis and improvement of code coverage.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.8
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• pp.763-767
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• 2008

In this paper, to make a high performance and low power CORDIC architecture for 3D operations in mobile devices, we suggest two off-line vectoring algorithms named Angle Based Search (ABS) and Scaling Considered Search (SCS). The ABS algorithm represents a 3D vector with two angles and those angles are used as a condition for searching CORDIC rotation sequences. The SCS algorithm determines the best CORDIC rotation sequence in advance to eliminate extra scaling computation. Using the proposed algorithms, we can observe 50% of latency is reduced. Furthermore, we perform a simple analysis and discuss possible reduction of power consumption by applying voltage scaling method together with the proposed algorithm.

• Journal of IKEEE
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• v.23 no.4
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• pp.1400-1407
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• 2019

In this paper, we propose a support vector machine (SVM) based gas classifier that can support real-time self-learning. The modified sequential minimal optimization (MSMO) algorithm is employed to train the proposed SVM. By using a shared structure for learning and classification, the proposed SVM reduced the hardware area by 35% compared to the existing architecture. Our system was implemented with 3,337 CLB (configurable logic block) LUTs (look-up table) with Xilinx Zynq UltraScale+ FPGA (field programmable gate array) and verified that it can operate at the clock frequency of 108MHz.