• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.1
• /
• pp.25-34
• /
• 2012

This paper presents a universal architecture for variable-length eight-parallel Reed-Solomon (RS) decoder for high-rate WPAN systems. The proposed architecture can support not only RS(255,239) code but various shortened RS codes. Moreover, variable-length architecture provides variable low latency for various shortened RS codes and the eight-parallel design also provides high data processing rate. Using 90-$nm$ CMOS standard cell technology, the proposed RS decoder has been synthesized and measured for performance. The proposed RS decoder can provide a maximum 19-$Gbps$ data rate at clock frequency 300 $MHz$.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.12C
• /
• pp.1207-1214
• /
• 2002

A scheduling scheme for high speed networks requires a low time complexity to schedule packets in a packet transmission time. High speed networks support a number of connections, different rates for each connection and variable packet length. Conventional round robin algorithms have a time complexity of O(1), but their short time fairness, latency and burstiness depend on the quantum of a connection due to serving several packets for a backlogged connection once a round. To improve these properties, we propose in this paper an efficient packet scheduling scheme which is based on the credits of a connection and has a time complexity of O(1). We also analyzed its performance in terms of short time fairness, latency and burstiness. The analysis results show that the proposed scheme can improve the performance compared with traditional round robin schemes. The proposed scheme can be easily utilized in high speed packet networks.

• Sleep Medicine and Psychophysiology
• /
• v.11 no.2
• /
• pp.80-83
• /
• 2004

Objectives: The multiple sleep latency test (MSLT) is commonly used as a valid objective measure of sleepiness. The procedure of MSLT is well standardized but the sleep onset criterion is somewhat variable. One epoch of stage 1 sleep is the most commonly used criterion, and the criterion of three epochs of stage 1 sleep is also used. The purpose of this study was to compare the two criteria used to determine sleep onset. Methods: We retrospectively analyzed 60 consecutive MSLT that were performed according to a standaridized protocol. We scored each test using the two different criteria for sleep onset and then statistically analyed the results. Results: Using the different criteria, 20 patients among 60 showed changes in mean sleep latency (33.3%). The extent of change ranged from 1.3% to 38.5% (mean 15.9%). Non-narcoleptic patients showed a significantly higher incidence of change than other sleep disorder patients. Conclusion: Changes in mean sleep latency occurred according to the different criteria of sleep onset. But the difference arising from different criteria was statistically not significant in patients with moderate to severe sleepiness. Considering that 1 epoch criterion for sleep onset is more sensitive in detecting clinically significant sleepiness, the authors suggest that the 1 epoch criterion is more reliable than the 3 epochs criterion.

• Archives of Craniofacial Surgery
• /
• v.19 no.3
• /
• pp.227-230
• /
• 2018

"Paraffinoma" is a well-recognized complication of paraffin oil injection into various body parts for an aesthetic purpose. After a variable latency phase, paraffinoma can present as a wide range of clinical symptoms. This paper is a case report of surgical excision of the paraffinoma and subsequent reconstruction of the associated skin defect on bilateral preauricular cheeks, manifesting 50 years after a primary injection.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.8 s.338
• /
• pp.35-42
• /
• 2005

This paper describes novel flip-flops with improved robustness and reduced power consumption. Variable sampling window flip-flop (VSWFF) adjusts the width of the sampling window according to input data, providing robust data latching as well as shorter hold time. The flip-flop also reduces power consumption for higher input switching activities as compared to the conventional low-power flip-flop. Clock swing-reduced variable sampling window flip-flop (CSR-VSWFF) reduces clock power consumption by allowing the use of a small swing clock. Unlike conventional reduced clock swing flip-flops, it requires no additional voltage higher than the supply voltage, eliminating design overhead related to the generation and distribution of this voltage. Simulation results indicate that the proposed flip-flops provide uniform latency for narrower sampling window and improved power-delay product as compared to conventional flip-flops. To evaluate the performance of the proposed flip-flops, test structures were designed and implemented in a $0.3\mu m$ CMOS process technology. Experimental result indicates that VSWFF yields power reduction for the maximum input switching activity, and a synchronous counter designed with CSR-VSWFF improves performance in terms of power consumption with no use of extra voltage higher than the supply voltage.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.4
• /
• pp.48-58
• /
• 2016

This paper presents the high-throughput fully-parallel architecture for GF(64) (160,80) regular (2,4) non-binary LDPC (NB-LDPC) codes decoder based on the extended min sum algorithm. We exploit the NB-LDPC code that features a very low check node and variable node degree to reduce the complexity of decoder. This paper designs the fully-parallel architecture and allows the interleaving check node and variable node to increase the throughput of the decoder. We further improve the throughput by the proposed early sorting to reduce the latency of the check node operation. The proposed decoder has the latency of 37 cycles in the one decoding iteration and achieves a high throughput of 1402Mbps at 625MHz.

• Journal of KIISE:Computer Systems and Theory
• /
• v.27 no.3
• /
• pp.287-299
• /
• 2000

In this paper, we classify multicast methods into three categories, i.e., tree-based, path-based, and hybrid-based multicasts, for a multicomputer employing the bidirectional torus network and wormhole routing. We propose the dynamic partition multicast routing (DPMR) as a path-based algorithm. As a hybrid-based algorithm, we suggest the hybrid multicast routing (HMR), which employs the tree-based approach in the first phase of routing and the path-based approach in the second phase. Performance is measured in terms of the average latency for various message length to compare three multicast routing algorithms. We also compare the performance of wormhole routing having variable buffer size with virtual cut-through switching. The message latency for each switching method is compared using the DPMR algorithm to evaluate the buffer size trade-off on the performance.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.1
• /
• pp.8-14
• /
• 2013

A low density parity check (LDPC) decoder provides a most powerful error control capability for mobile communication devices and storage systems, due to its performance being close to Shannon's limit. In this paper, we introduce an efficient overlapped LDPC decoding algorithm using a upper dual-diagonal parity check matrix structure. By means of this algorithm, the LDPC decoder can concurrently execute parts of the check node update and variable node update in the sum-product algorithm. In this way, we can reduce the number of clock cycles per iteration as well as reduce the total latency. The proposed decoding structure offers a very simple control and is very flexible in terms of the variable bit length and variable code rate. The experiment results show that the proposed decoder can complete the decoding of codewords within 70% of the number of clock cycles required for a conventional non-overlapped decoder. The proposed design also reduces the power consumption by 33% when compared to the non-overlapped design.

• Journal of Korea Multimedia Society
• /
• v.9 no.8
• /
• pp.1020-1029
• /
• 2006

Realization of high-capacity quality-of-service router needs fair packet schedulers with a lower complexity. Timestamp based fair packet schedulers have the ideal complexity of O(log V), where V is the maximum number of admitted flows, but it has been recently reduced to O(1) using bin concept. However, the latency property was deteriorated and the bandwidth utilization was also declined. In addition, traffic flows requiring strong delay bound may not be admitted. To overcome these problems, this paper proposes a Mini-Bin based Start-Time (MBST) scheduler with variable complexity and evaluates its performance. The MBST scheduler uses the timestamp calculation scheme of start-time based schedulers to enhance the bandwidth utilization and also introduces mini-bin concept to improve the latency, The performance evaluation shows that the proposed scheduler can reduce the complexity of the legacy start-tine based schedulers by $1.8{\sim}5$ times without deteriorating the bandwidth utilization property.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.11 no.2
• /
• pp.67-78
• /
• 2016

The emerging Spin-Transfer Torque RAM (STT-RAM) is a promising component that can be used to improve the efficiency as a result of its high storage density and low leakage power. However, the state-of-the-art STT-RAM is not ready to replace SRAM technology due to the negative effect of its write operations. The write operations require longer latency and more power than the same operations in SRAM. Therefore, a hybrid cache with SRAM and STT-RAM technologies is proposed to obtain the benefits of STT-RAM while minimizing its negative effects by using SRAM. To efficiently use of the hybrid cache, it is important to place write intensive data onto the cache. Such data should be placed on SRAM to minimize the negative effect. Thus, we propose a technique that optimizes placement of data in main memory. It drives the proper combination of advantages and disadvantages for SRAM and STT-RAM in the hybrid cache. As a result of the proposed technique, write intensive data are loaded to SRAM and read intensive data are loaded to STT-RAM. In addition, our technique also optimizes temporal locality to minimize conflict misses. Therefore, it improves performance and energy consumption of the hybrid cache architecture in a certain range.