• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.281.2-281.2
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• 2016

Two-dimensional van der Waals (2D vdWs) materials have been extensively studied for future electronics and materials sciences due to their unique properties. Among them, black phosphorous (BP) has shown infinite potential for various device applications because of its high mobility and direct narrow band gap (~0.3 eV). In this work, we demonstrate a few-nm thick BP-based nonvolatile memory devices with an well-known poly(vinylidenefluoride-trifluoroethylene) [P(VDF-TrFE)] ferroelectric polymer gate insulator. Our BP ferroelectric memory devices show the highest linear mobility value of $1159cm^2/Vs$ with a $10^3$ on/off current ratio in our knowledge. Moreover, we successfully fabricate the ferroelectric complementary metal-oxide-semiconductor (CMOS) memory inverter circuits, combined with an n-type $MoS_2$ nanosheet transistor. Our memory CMOS inverter circuits show clear memory properties with a high output voltage memory efficiency of 95%. We thus conclude that the results of our ferroelectric memory devices exhibit promising perspectives for the future of 2D nanoelectronics and material science. More and advanced details will be discussed in the meeting.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.286-286
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• 2010

The lack of homogeneously sized single-walled carbon nanotubes (SWNTs) hinders their many applications because properties of SWNTs, in particular electrical conduction, are highly dependent on the diameter and chirality. Therefore, the preferential growth of SWNTs with predetermined diameters is an ultimate objective for applications of SWNTs-based nanoelectronics. It has been previously emphasized that a catalyst size is the one crucial factor to determine the CNTs diameter in chemical vapor deposition (CVD) process, giving rise to several attempts to obtain size-controllable catalyst by diverse methods, such as solid supported catalyst, metal-containing molecular nanoclusters, and nanostructured catalytic layer. In this work, diameter-controlled CNTs were synthesized using a nanostructured catalytic layer consisting of Fe/Al2O3/Si substrate. The CNTs diameter was controlled by structural modification of Al2O3 supporting layer, because Al2O3 supporting layer can affect agglomeration phenomenon induced by heat-driven surface diffusion of Fe catalytic nanoparticles at growth temperature.

• Journal of the Korean Vacuum Society
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• v.20 no.4
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• pp.294-299
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• 2011

In this study, single-walled carbon nanotubes (SWCNTs) were synthesized on a Fe/$Al_2O_3$/Si layer by thermal chemical vapor deposition. Metallic SWCNTs were selectively removed by microwave irradiation. Electrical and structural characterizations of the SWCNTs clearly revealed that the metallic SWCNTs were almost removed by microwave irradiation for 120 sec. The remained semiconducting SWCNTs with a high crystalline structure were obtained over 95%. This method would provide useful information for applications to SWCNTs-based field effect transistors and multifaceted nanoelectronics.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.490-490
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• 2011

Graphene, hexagonal network of carbon atoms forming a one-atom thick planar sheet, has been emerged as a fascinating material for future nanoelectronics. Huge attention has been captured by its extraordinary electronic properties, such as bipolar conductance, half integer quantum Hall effect at room temperature, ballistic transport over ${\sim}0.4{\mu}m$ length and extremely high carrier mobility at room temperature. Several approaches have been developed to produce graphene, such as micromechanical cleavage of highly ordered pyrolytic graphite using adhesive tape, chemical reduction of exfoliated graphite oxide, epitaxial growth of graphene on SiC and single crystalline metal substrate, and chemical vapor deposition (CVD) synthesis. In particular, direct synthesis of graphene using metal catalytic substrate in CVD process provides a new way to large-scale production of graphene film for realization of graphene-based electronics. In this method, metal catalytic substrates including Ni and Cu have been used for CVD synthesis of graphene. There are two proposed mechanism of graphene synthesis: carbon diffusion and precipitation for graphene synthesized on Ni, and surface adsorption for graphene synthesized on Cu, namely, self-limiting growth mechanism, which can be divided by difference of carbon solubility of the metals. Here we present that large area, uniform, and layer controllable graphene synthesized on Cu catalytic substrate is achieved by acetylene-assisted CVD. The number of graphene layer can be simply controlled by adjusting acetylene injection time, verified by Raman spectroscopy. Structural features and full details of mechanism for the growth of layer controllable graphene on Cu were systematically explored by transmission electron microscopy, atomic force microscopy, and secondary ion mass spectroscopy.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.499-499
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• 2011

Silicon nanowires (Si NWs) have been extensively studied for nanoelectronics owing to their unique optical and electrical properties different from those of bulk silicon. For the development of Si NW devices, better understanding of oxidation behavior in Si NWs would be an important issue. For example, it is widely known that atomic scale roughness at the dielectric (SiOx)/channel (Si) interface can significantly affect the device performance in the nano-scale devices. However, the oxidation process at the atomic-scale is still unknown because of its complexity. In the present work, we investigated the oxidation behavior of Si NW in atomic scale by simulating the dry oxidation process using a reactive molecular dynamics simulation technique. We focused on the residual stress evolution during oxidation to understand the stress effect on oxidation behavior of Si NWs having two different diameters, 5 nm and 10 nm. We calculated the charge distribution according to the oxidation time for 5 and 10 nm Si NWs. Judging from this data, it was observed that the surface oxide layer started to form before it is fully oxidized, i.e., the active diffusion of oxygen in the surface oxide layer. However, it is well-known that the oxide layer formation on the Si NWs results in a compressive stress on the surface which may retard the oxygen diffusion. We focused on the stress evolution of Si NWs during the oxidation process. Since the surface oxidation results in the volume expansion of the outer shell, it shows a compressive stress along the oxide layer. Interestingly, the stress for the 10 nm Si NW exhibits larger compressive stress than that of 5 nm Si NW. The difference of stress level between 5 an 10 anm Si NWs is approximately 1 or 2 GPa. Consequently, the diameter of Si NWs could be a significant factor to determine the self-limiting oxidation behavior of Si NWs when the diameter was very small.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.208-208
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• 2013

Graphene has emerged as a fascinating material for next-generation nanoelectronics due to its outstanding electronic properties. In particular, graphene-based field effect transistors (GFETs) have been a promising research subject due to their superior response times, which are due to extremely high electron mobility at room temperature. The biggest challenges in GFET applications are control of carrier concentration and opening the bandgap of graphene. To overcome these problems, three approaches to doping graphene have been developed. Here we demonstrate the decoration of Ni nanoparticles (NPs) on graphene films by simple annealing for p-type doping of graphene. Ni NPs/graphene films were fabricated by coating a $NiCl2{\cdot}6H2O$ solution onto graphene followedby annealing. Scanning electron microscopy and atomic force microscopy revealed that high-density, uniformly sized Ni NPs were formed on the graphene films and the density of the Ni NPs increased gradually with increasing $NiCl2{\cdot}6H2O$ concentration. The formation of Ni NPs on graphene films was explained by heat-driven dechlorination and subsequent particlization, as investigated by X-ray photoelectron spectroscopy. The doping effect of Ni NPs onto graphene films was verified by Raman spectroscopy and electrical transport measurements.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.362-362
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• 2014

Atomic layer deposition (ALD) can be regarded as a special variation of the chemical vapor deposition method for reducing film thickness. ALD is based on sequential self-limiting reactions from the gas phase to produce thin films and over-layers in the nanometer scale with perfect conformality and process controllability. These characteristics make ALD an important film deposition technique for nanoelectronics. Tantalum pentoxide ($Ta_2O_5$) has a number of applications in optics and electronics due to its superior properties, such as thermal and chemical stability, high refractive index (>2.0), low absorption in near-UV to IR regions, and high-k. In particular, the dielectric constant of amorphous $Ta_2O_5$ is typically close to 25. Accordingly, $Ta_2O_5$ has been extensively studied in various electronics such as metal oxide semiconductor field-effect transistors (FET), organic FET, dynamic random access memories (RAM), resistance RAM, etc. In this experiment, the variations of chemical and interfacial state during the growth of $Ta_2O_5$ films on the Si substrate by ALD was investigated using in-situ synchrotron radiation photoemission spectroscopy. A newly synthesized liquid precursor $Ta(N^tBu)(dmamp)_2$ Me was used as the metal precursor, with Ar as a purging gas and $H_2O$ as the oxidant source. The core-level spectra of Si 2p, Ta 4f, and O 1s revealed that Ta suboxide and Si dioxide were formed at the initial stages of $Ta_2O_5$ growth. However, the Ta suboxide states almost disappeared as the ALD cycles progressed. Consequently, the $Ta^{5+}$ state, which corresponds with the stoichiometric $Ta_2O_5$, only appeared after 4.0 cycles. Additionally, tantalum silicide was not detected at the interfacial states between $Ta_2O_5$ and Si. The measured valence band offset value between $Ta_2O_5$ and the Si substrate was 3.08 eV after 2.5 cycles.