• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.49-53
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• 2023

In this paper, we propose an antirandom pattern-based test method considering power consumption to compensate for the problem that the fault coverage through random test decreases or the test time increases significantly when the DUT circuit structure is complex or large. In the proposed method, a group unit test pattern generation process and rearrangement process are added to improve the problems of long calculation time and high-power consumption, which are disadvantages of the previous antirandom test.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.74-83
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• 2002

In order to design a huge VLSI system, the scan testing methodology by employing scan flip-flops(cells) is a popular method to test those If chips. In this case, the connection order of scan cells are not important, and hence the order can be determined in the very final stage of physical design such as cell placement. Using this fact, we propose, in this paper, a scan cell reordering method which minimizes the length of wires for scan chain connections. Especially, our reordering method is newly proposed method in the case when the scan cells are grouped according to their clock domains. In fact, the proposed reordering method reduces the wire length about 13.6% more than that by previously proposed reordering method. Our method may also be applicable for reordering scan chains that have various constraints on the scan cell locations due to the chain grouping.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.28-36
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• 2002

As cross-coupling capacitance generated in transmission line has been an important issue in VLSI world, a couple of ATPG algorithms has been proposed. However they were studied only for a simple single-line effect problem, so it cost so much time for an unsatisfying test generation efficiency. In this paper, we studied a noise model for multiple affected lines and generated test patterns in a short time. This paper proposes a crosstalk model affected by multiple tranmission lines and implemented an ATPG algorithm for detection of crosstalk noise faults. We modeled the crosstalk noise by multiple transmission line and made a truth table for this. We implemented an ATPG algorithm based on PODEM and revealed the results.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.1667-1670
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• 2005

본 논문에서는 차세대 통신 플랫폼을 위한 PCI Express의 전송계층과 데이터 연결계층의 모든 기능을 지원하는 PCI Express 컨트롤러를 설계하였다. 설계되어진 컨트롤러는 재전송 매커니즘을 효과적으로 지원하기 위해 제안되어진 송신버퍼 구조를 가지고 있다. 이 버퍼 구조는 전송 버퍼와 재전송 버퍼를 한 개의 버퍼로 통합하여 재전송 버퍼의 공간을 유동적으로 할당할 수 있는 방법이다. 또한 설계되어진 컨트롤러의 송신단 전송계층은 제안되어진 버퍼 구조 효과적으로 지원하도록 설계되어 졌다. 설계 되어진 컨트롤러의 각 블록을 효과적으로 관리하기 위해 80C51 마이크로프로세서를 내장하여 PCI Express 프로토콜을 제공하는 프로그램을 코딩하여 포팅하였다. 또한 설계되어진 컨트롤러의 검증을 위해, Host Bridge, 로컬 마스터 디바이스, 로컬 슬레이브 디바이스를 버스 동작 모델로 구성된 테스트 벤치도 제안하였다. 또한 실제 PCI Express 프로토콜 상에서 발생할 수 있는 모든 경우를 발생 하도록 하기 위해, 각 버스 동작 모델을 위한 어셈블러 명령어들을 정의 하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.9
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• pp.78-85
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• 2000

A new analytical VLSI interconnect delay model is presented and its accuracy is experimentally verified. In the model, the transmission line parameter variations due to skin effect, proximity effect, and silicon substrate effect are taken into account. That is, the circuit model of the interconnect line that includes these effects is newly developed and analyzed. For the model verification, test patterns combined the coplanar structure with microstrip were designed by using 0.35${\mu}m$ CMOS process technology. It is shown that the accuracy of the model is less than about 10% error.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.85-97
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• 2002

STUMPS has been widely used for built-in self-test of scan design with multiple scan chains. In the STUMPS architecture, there is very high correlation between the bit sequences in the adjacent scan chains. This correlation causes circuits lower the fault coverage. In order to solve this problem, an extra combinational circuit block(phase shifter) is placed between the LFSR and the inputs of STUMPS architecture despite the hardware overhead increase. This paper introduces an efficient test pattern generation technique and built-in self-test architecture for sequential circuits with multiple scan chains. The proposed test pattern generator is not used the input of LFSR and phase shifter, hence hardware overhead can be reduced and sufficiently high fault coverage is obtained. Only several XOR gates in each scan chain are required to modify the circuit for the scan BIST, so that the design is very simple.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.8
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• pp.86-96
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• 2000

The representative area among the ones whose cost increases as the integration ratio increases is the test area. As the relative cost of hardware decreases, the BIST method has been focued on as the future-oriented test method. The biggest drawback of it is the increasing test time to obtain the acceptable fault coverage. This paper proposed a BIST implementation method to reduce the test times. This method uses an input grouping and test point insertion method, in which the definition of test point is different from the previous one. That is, the test points are defined on the basis of the internal nodes which are the reference points of the input grouping and are merging points of the grouped signals. The main algorithms in the proposed method were implemented with C-language, and various circuits were used to apply the proposed method for experiment. The results showed that the test time could be reduced to at most $1/2^{40}$ of the pseudo-random pattern case and the fault coverage were also increased compared with the conventional BIST method. The relative hardware overhead of the proposed method to the circuit under test decreases as th e size of the circuit to be tested increases, and the delay overhead by the BIST utility is negligible compared to that of the original circuit. That means, the proposed method can be applied efficiently to large VLSI circuits.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.8-21
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• 1997

In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in MOS FETs included in typical memory cell of VLSI SRAM and analyze behavior of memory by using PSPICE simulation. Using conventional fault models and this behavioral analysis, we propose linear testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ (quiescent power supply current) testing simultaneously to improve functionality and reliability of memory. Finally, we implement BIST (built-in self tsst) circuit and BICS(built-in current sensor), which are embedded on memory chip, to carry out functional testing efficiently and to detect various defects at high-speed respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.24-24
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• 2001

빠른 반도체 기술의 발전으로 인하여 VLSI 회로의 복잡도는 크게 증가하고 있다. 그래서 복잡한 회로를 테스팅하는 것은 아주 어려운 문제로 대두되고 있다. 또한 집적회로의 증가된 집적도로 인하여 여러 가지 형태의 고장이 발생하게 됨으로써 테스팅은 더욱 중요한 문제로 대두되고 있다. 이제까지 일반적으로 지연 고장 테스팅에 대한 신뢰도는 가정된 고장의 개수에 대한 검출된 고장의 개수로 표현되는 전통적인 고장 검출율로서 평가되었다. 그러나 기존의 교장 검출율은 고장 존재의 유무만을 고려한 것으로써 실제의 지연 고장 테스팅에 대한 신뢰도와는 거리가 있다. 지연 고장 테스팅은 고착 고장과는 달리 경로의 진행 지연과 지연 결함 크기 그리고 시스템 동작 클럭 주기에 의존하기 때문이다. 본 논문은 테스트 중인 경로의 진행 지연과 지연 결함 크기를 고려한 새로운 고장 검출율 메트릭으로서지연 결함 고장 검출율(delay defect fault coverage)을 제안하였으며, 지연 결함 고장 검출율과 결함 수준(defect level)과의 관계를 분석하였다

• The Transactions of the Korea Information Processing Society
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• v.6 no.3
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• pp.766-772
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• 1999

With the increase of portable system and high-density IC, power consumption of VLSI circuits is very important factor in design process. Power estimation is required in order to estimate the power consumption. A simple and correct solution of power estimation is to use circuit simulation. But it is very time consuming and inefficient way. Probabilistic method has been proposed to overcome this problem. Transition density using probability was an efficient method to estimate power consumption using BDD and Boolean difference. But it is difficult to build the BDD and compute complex Boolean difference. In this paper, we proposed Propowest. Propowest is building a digraph of circuit, and easy and fast in computing transition density by using modified COP algorithm. Propowest provides an efficient way for power estimation.