• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.57-66
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• 2014

This paper presents a low-complexity barrel distortion correction processor for wide-angle cameras. The proposed processor performs the barrel distortion correction jointly with the color demosaicking, so that the hardware complexity can be reduced significantly. In addition, to reduce the required memory bandwidth, an efficient memory interface is proposed by utilizing the spatial locality of the memory access in the correction process. The proposed processor is implemented with 35K logic gates in a $0.11-{\mu}m$ CMOS process and its correction speed is 150 Mpixels/s at the operating frequency of 606MHz, where the supported frame size is $2048{\times}2048$ and the required memory bandwidth is 1 read/cycle.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.2
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• pp.105-111
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• 2024

This paper deals with the minimum linear arrangement(MinLA) of a lattice graph, to which an approximate algorithm of linear complexity O(n) remains as a viable solution, deriving the optimal MinLA of 31,680 for 33×33 lattice. This paper proposes a partitioning arrangement algorithm of complexity O(1) that delivers exact solution to the minimum linear arrangement. The proposed partitioning arrangement algorithm could be seen as loading boxes into a container. It firstly partitions m rows into r₁,r₂,r₃ and n columns into c₁,c₂,c₃, only to obtain 7 containers. Containers are partitioning with a rule. It finally assigns numbers to vertices in each of the partitioned boxes location-wise so as to obtain the MinLA. Given m,n≥11, the size of boxes C₂,C₄,C₆ is increased by 2 until an increase in the MinLA is detected. This process repeats itself 4 times at maximum given m,n≤100. When tested to lattice in the range of 2≤n≤100, the proposed algorithm has proved its universal applicability to lattices of both m=n and m≠n. It has also obtained optimal results for 33×33 and 100×100 lattices superior to those obtained by existing algorithms. The minimum linear arrangement algorithm proposed in this paper, with its simplicity and outstanding performance, could therefore be also applied to the field of Very Large Scale Integration circuit where m,n are infinitely large.