• 한국통신학회논문지
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• 제18권10호
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• pp.1553-1571
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• 1993

전형적인 컬퓨터보다 훨씬 강력한 계산 능력을 얻기 위해 병렬 컴퓨터 구조에 대한 많은 연가 진행되어 왔다. 이러한 컴퓨터들은 통상 상호 연결 네트워크(Interconnection Network)로 연결된 많은 수의 처리기들로 구성된다. 그중 중요한 한 부류가 초대규모 집적(Very Large Scale Integration) 또는 웨이퍼규모 집적(Wafer Scale Integration)을 이용한 셀룰러 병렬 처리기로 하나의 칩이나 웨이퍼에 단지 이웃으로만 연결된 많은 수의 단순 조를 가지는 처리기로 구성된다. 이런 셀룰러 병렬 처리기틀에 반드시 수반되는 문제가 재구현(Reconfiguration)으로 세가지 유형을 정의할 수 있는데 본 논문에서는 이 세가지 재구현 문제, 즉 결함 허용 재구현(Fault-Tolerant Reconfiguration), 기능적 재구현(Functional Reconfiguration), 그리고 통합 재구현(Integrated Reconfiguration)에 대하여 논하였다. 본 논문은 결함 진단 및 검출(Fault Detection and Fault Location) 제어 방법, 구성(Configuration) 제어방법, 재구현의 수행 단계 등 결함 허용 재구현과 기능적 재구현시 필요한 여러 고려 사항을 분석 정리하고, 최근 제기된 결함 허용 재구현과 기능적 재구현의 일체화 문제 즉 통합 재구현 문제의 이해에 핵심적인 결할 허용 재구현과 기능적 재구현 사이의 관계를 밝혔으며, 통합 재 구현에 적합한 결할 진단 및 검출 제어 방법과 구성제어 방법에 대하여 논하였다.

• Journal of Communications and Networks
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• 제11권1호
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• pp.20-25
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• 2009

The maximum likelihood detection with QR decomposition and M-algorithm (QRM-MLD) has been presented as a suboptimum multiple-input multiple-output (MIMO) detection scheme which can provide almost the same performance as the optimum maximum likelihood (ML) MIMO detection scheme but with the reduced complexity. However, due to the lack of parallelism and the regularity in the decoding structure, the conventional QRM-MLD which uses the tree-structure still has very high complexity for the very large scale integration (VLSI) implementation. In this paper, we modify the tree-structure of conventional QRM-MLD into trellis-structure in order to obtain high operational parallelism and regularity and then apply the Viterbi algorithm to the QRM-MLD to ease the burden of the VLSI implementation.We show from our selected numerical examples that, by using the QRM-MLD with our proposed trellis-structure, we can reduce the complexity significantly compared to the tree-structure based QRM-MLD while the performance degradation of our proposed scheme is negligible.

• ETRI Journal
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• 제32권3호
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• pp.380-389
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• 2010

This paper presents a new edge-protection algorithm and its very large scale integration (VLSI) architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge-protection maps. Based on these maps, a two-step adaptive filter which includes offset filtering and edge-preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory-reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is verified on FPGA Cyclone II and implemented using the ANAM 0.25 ${\mu}m$ CMOS cell library. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details. The PSNR performance of our algorithm using pixel classification is better than that of previous algorithms using block classification.

• 한국시뮬레이션학회논문지
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• 제18권4호
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• pp.59-66
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• 2009

VLSI(Very Large Scale Integration)와 WSI(Wafer Scale Integration)와 같은 통합기술로 인해 큰 용량의 메모리 대량생산이 가능 하게 된 지금 Redundancy는 메모리 칩의 제조와 결함이 있는 셀을 지닌 디바이스를 치료하는데 광범위하게 사용되어져왔다. 메모리칩의 밀도가 증가함에 따라 결함의 빈도 또한 증가한다. 많은 결함이 있다면 어쩔 수 없겠지만 적은 결함이 발생한 경우에는 해당 다이를 reject 시키는 것 보다는 수선해서 사용하는 것이 메모리생산 업체 입장에서는 보다 효율적이고 원가 절감 차원에서 필수적이다. 이와 같은 이유로 laser repair라는 공정이 필요하고 laser repair공정의 정확한 타깃을 설정하기 위해 redundancy analysis가 필요하게 되었다. CRA시뮬레이션은 기존의 redundancy analysis 알고리즘의 개념에서 벗어나 결함 유형별로 시뮬레이션한 후 RA를 진행함으로써 RA에 소요되는 시간을 절약함으로써 원가 경쟁력 강화를 할 수 있다.

• 한국품질경영학회:학술대회논문집
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• 한국품질경영학회 1998년도 The 12th Asia Quality Management Symposium* Total Quality Management for Restoring Competitiveness
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• pp.393-403
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• 1998

The advent of very large scale integration(VLSI) has had a tremendous impact on the design of fault-tolerant circuits and systems. The increasing density, decreasing power consumption, and decreasing costs of integrated circuits, due in part to VLSI, have made it possible and practical to implement the redundancy approaches used in fault-tolerant computing. The purpose of this paper is to study the many aspects of designing fault-tolerant systems in a VLSI environment. First, we expound upon the opportunities and problemes presented by VLSI technology. Second, we consider in detail the importance of design mistakes, common-mode failures, and transient faults in VLSI. Finally, we examine the techniques available to implement redundancy using VLSI and the problems associated with these techniques.

• 산업경영시스템학회지
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• 제22권53호
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• pp.111-120
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• 1999

The advent of very large scale integration(VLSI) has had a tremendous impact on the design of fault-tolerant circuits and systems. The increasing density, decreasing power consumption, and decreasing costs of integrated circuits, due in part to VLSI, have made it possible and practical to implement the redundancy approaches used in fault-tolerant computing. The purpose of this paper is to study the many aspects of designing fault-tolerant systems in a VLSI environment. First, we expound upon the opportunities and problems presented by VLSI technology. Second, we consider in detail the importance of design mistakes, common-mode failures, and transient faults in VLSI. Finally, we examine the techniques available to implement redundancy using VLSI and the promlems associated with these techniques.

• ETRI Journal
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• 제43권2호
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• pp.260-271
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• 2021

This paper addresses Very large-scale integration (VLSI) placement optimization, which is important because of the rapid development of VLSI design technologies. The goal of this study is to develop a hybrid algorithm for VLSI placement. The proposed algorithm includes a sequential combination of a genetic algorithm and an evolutionary algorithm. It is commonly known that local search algorithms, such as random forest, hill climbing, and variable neighborhoods, can be effectively applied to NP-hard problem-solving. They provide improved solutions, which are obtained after a global search. The scientific novelty of this research is based on the development of systems, principles, and methods for creating a hybrid (combined) placement algorithm. The principal difference in the proposed algorithm is that it obtains a set of alternative solutions in parallel and then selects the best one. Nonstandard genetic operators, based on problem knowledge, are used in the proposed algorithm. An investigational study shows an objective-function improvement of 13%. The time complexity of the hybrid placement algorithm is O(N2).

• Journal of Electrical Engineering and Technology
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• 제3권1호
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• pp.130-134
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• 2008

The increasing size of very large scale integration (VLSI) circuits, high transistor density, and popularity of low-power circuit and system design are making the minimization of power dissipation an important issue in VLSI design. Test Power dissipation is exceedingly high in scan based environments wherein scan chain transitions during the shift of test data further reflect into significant levels of circuit switching unnecessarily. Scan chain or cell modification lead to reduced dissipations of power. The ETC algorithm of previous work has weak points. Taking all of this into account, we therefore propose a new algorithm. Its name is RE_ETC. The proposed modifications in the scan chain consist of Exclusive-OR gate insertion and scan cell reordering, leading to significant power reductions with absolutely no area or performance penalty whatsoever. Experimental results confirm the considerable reductions in scan chain transitions. We show that modified scan cell has the improvement of test efficiency and power dissipations.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권3호
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• pp.133-139
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• 2007

Future MEMS systems will be composed of larger varieties of devices with very different functionality such as electronics, mechanics, optics and bio-chemistry. Integration technology of heterogeneous devices must be developed. This article first deals with the current development trend of new fabrication technologies; those include self-assembling of parts over a large area, wafer-scale encapsulation by wafer-bonding, nano imprinting, and roll-to-roll printing. In the latter half of the article, the concept towards the heterogeneous integration of devices and functionality into micro/nano systems is described. The key idea is to combine the conventional top-down technologies and the novel bottom-up technologies for building nano systems. A simple example is the carbon nano tube interconnection that is grown in the via-hole of a VLSI chip. In the laboratory level, the position-specific self-assembly of nano parts on a DNA template was demonstrated through hybridization of probe DNA segments attached to the parts. Also, bio molecular motors were incorporated in a micro fluidic system and utilized as a nano actuator for transporting objects in the channel.

• 대한전자공학회논문지SD
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• 제45권6호
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• pp.104-110
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• 2008

본 논문에서는 새로운 2레벨 탐색 스피어 디코딩 알고리즘과 그 하드웨어 구조를 제안한다. 제안된 알고리즘은 심볼검출 시에 성능향상에 영향을 줄 수 있는 유용한 후보군이 이전 단계에서 버려지는 것을 피하기 위해서, 2 레벨 트리탐색을 동시에 수행한다. 시뮬레이션 결과, 제안된 알고리즘이 BER 측면에서 기존의 알고리즘보다 성능이 우수함을 확인할 수 있었다. 제안된 하드웨어 구조는 낮은 복잡도와 고정된 throughput을 갖는 구조로써 BPSK, QPSK, 16-QAM, 64-QAM의 변조방식을 지원한다. 하드웨어 측면에서 큰 복잡도를 갖는 정렬 블럭은 다른 블럭과 하드웨어를 공유함으로써 면적을 감소시켰고, 제안된 하드웨어 구조는 기존의 구조들과 비교했을 때 면적이 감소되고 성능이 향상됨을 확인하였다.