• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.1
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• pp.104-112
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• 1989

A design automation method for sequential circuits implementation by mans of PLA is discussed, and an optimal state-code assignment algorithm to minimize the PLA area is proposed. In order to design sequential circuit automatically, DASL (Design Automation Support Language) [8] which is easy to describe and powerful to synthesize, is proposed and used to describe sequential circuit, An optimal statecode assignment algorithm which considers next states and outputs simultaneously is proposed, and by adopting this algorithm to various examples, the area of PLA is reduced by 10% comparing privious methods. This system is constructed to design microinstruction, FSM, VLSI control part synthesis.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.247-250
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• 2000

본 논문에서는 MPEG-2 AAC 오디오 복호화 시스템을 효율적으로 설계하고 구현하였다. 구현된 시스템은 2채널의 메인 프로필 MPEG-2 AAC 비트열을 실시간으로 복호화하고, 32, 44.1, 48kHz의 표본화 주파수를 지원하여, 표준안에서 제안하는 툴 중 커플링 채널을 제외한 모든 툴을 지원한다. 설계된 시스템은 허프만 복호화와 예측 과정을 수행하는 두개의 독립된 모듈과 Programmable DSP 코어의 혼합 구조(hybrid architecture)로 최적화된 구조를 갖는다.

• Proceedings of the Korea Multimedia Society Conference
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• 2002.11b
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• pp.545-548
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• 2002

본 논문에서는 유리 B 스플라인 곡선을 이용한 블록 효과 감소 알고리듬을 VHDL을 이용하여 설계하고, 모의 실험을 통하여 동작을 확인한다. 블록 효과는 매우 낮은 비트율로 블록 기반 부호화 방식을 수행할 때 복원 영상에서 나타나는 블록 형태의 왜곡을 의미한다. 설계된 회로는 유리 B 스플라인 곡선을 적용한 블록 효과 감소 알고리듬으로서, 이 기법은 컴퓨터 그래픽스 분야에서 제어점을 근사하는 부드러운 곡선을 생성하기 위해 사용되는 스플라인 곡선을 적용하여 블록 현상을 효과적으로 감소시킨다. 설계된 회로는 주파수 100MHz에서 동작을 시켰으며, 모의 실험 결과 매우 우수한 블록 효과 감소 기능을 가진 것을 알 수 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.1
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• pp.58-70
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• 1990

This paper describes a VLSI implementation of real-time two dimensional DCT processor for the subprimary rate video codec system. The proposed architecture exploits the parallelism and concurrency of the distributes architecture for vector inner product operation of DCT and meets the CCITT performance requirements of video codec for full CSIF 30 frames/sec. It is also shown that this architecture satisfies all the CCITT IDCT accuracy specification by simulating the suggested architecture in bit level. The efficient VLSI disign methodology to design suggested architecture is considered and the module generator oriented design environments are constructed based on SUN 3/150C workstation. Using the constructed design environments. the suggensted architecture have been designed by double metal 2micron CMOS technology. The chip area fo designed 8x8 2-D DA-DCT (Distributed Arithmetic DCT) processor is about 3.9mmx4.8mm.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.3_4
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• pp.160-169
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• 2004

With an emergence of SOC from developed IC technology, the VLSI design has required the core re-use technique and modular test development. To minimize the cost of testing SOC, an efficient method is required to optimize the test time and area overhead in conjunction for the core test wrapper, which is one of the important elements for SOC test architecture. In this paper, we propose an efficient design strategy of core test wrapper to achieve the minimum cost for SOC testing. The proposed strategy adopted advantages of traditional methods and more developed to be successfully used in practice.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.5
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• pp.477-485
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• 2002

In this paper, we present an efficient hardware architecture for the H.263 video codec and its VLSI implementation. This architecture is based on the unified interface by which internal hardware engines and an internal RISC processor are connected one another. The unified interface enables the modular design of internal blocks, efficient hardware/software partitioning, and pipelined paralled operations. The developed VLSI supports the H.263 version 2 profile 3 @ level 10, and moreover, both the control protocol H.245 and the multiplexing protocol H.223. Therefore, it can be used for the complete ITU-T H.324 or 3GPP 3G 324M multimedia processor with the help of an external audio codec. Simultaneous encoding and decoding of QCIF format images at a rate greater than 15 frames per second is achieved at 40 MHz clock frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.265-268
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• 2001

In this paper, we designed one-dimensional VLSI array with high speed processing in Fractal image compression. fractal image compression algorithm partitions the original image into domain blocks and range blocks then compresses data using the self similarity of blocks. The image is partitioned into domain block with 50% overlapping. Domain block is reduced by averaging the original image to size of range block. VLSI array is trying to search the best matching between a range block and a large amount of domain blocks. Adjacent domain blocks are overlapped, so we can improve of each block's processing speed using the reuse of the overlapped data. In our experiment, proposed VLSI array has about 25% speed up by adding the least register, MUX, and DEMUX to the PE.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.9
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• pp.76-84
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• 1994

This paper presents a new high-performance VLSI architecture and VLSI implementation for full-search block matching algorithm. The proposed VLSI architecture has the feature of two directional parallel and pipeline processing, thereby reducing the PE idle time at which the direction of block matching operation within the search area is changed. Therfore, the proposed architecture is faster than the existing architectures under the same clock frequency. Based on HSPICE circuit simulation, it is verified that the implemented procesing element is operated successfully within 13 ns for 75 MHz operation.

• The Journal of Natural Sciences
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• v.8 no.2
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• pp.69-75
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• 1996

This paper presents a VLSI architecture for the efficient implementation of the real time multi-dimensional digital filter. The computational primitive for the filter is obtained from the state space representation of the multi-dimensional general order filter. The computational primitive is used for the data path of the processor.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.8
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• pp.998-1009
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• 1988

A Hierarchical Circuit Extract Algotithm, which efficiently extract circuits from VLSI mask pattern information, is programmed. Quad-tree is used as a data structure which includes various CIF circuit elements and instances. This system is composed of CIF input routine, Quad-tree making routine, Transistor finding routine and Connection list making routine. This circuit extractor can extract circuit with hierarchical structure of circuit. This system is designed using YACC and LEX. By programming this algorithm with C language and adopting to various circuits, the effectiveness of this algorithm is showed.