• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.863-866
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• 1999

In this paper, we designed a Viterbi decoder with constraint length K=7, code rate R=1/2, encoder generator polynomial (171, 133)$_{8}$. This decoder makes use of 3-bit soft decision. We designed the Viterbi decoder using VHDL. We employed conventional logic circuit instead of ROM for branch metric units(BMUs) to reduce the number of gates. We adopted fully parallel structures for add-compare-select units(ACSUs). The size of the designed decoder is about 200, 000 gates.s.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2002.11a
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• pp.468-478
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• 2002

고품질의 영상 압축기인 JPEG2000의 기본 압축 코덱인 EBCOT(Embedded Block Coding With Optimized Truncation)를 설계하였다. 영상 압축기에서 Context 추출 구현을 위하여 코드블록(Code block)으로 분할하고, 비트플랜(Bit-Plane)코딩을 했으며, 3가지 패스 그룹으로 분리한 후 ZC, RLC, MR, SC를 하였다. 산술부호화는 덧셈 연산과 쉬프트 연산만을 사용하는 MQ-coder를 사용하였으며, Context들의 누적 확률을 추정하여 테이블을 작성하였고, 압축데이터를 산출하였다. 영상 압축을 위한 엔트로피 코더의 하드웨어 구현은 VHDL를 이용하여 설계를 하고, Synopsys사의 논리 회로 합성 도구를 사용하여 합성을 하였으며, Altera사의 FLEX 10K250 Device를 이용하여 FPGA로 구현하였다.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.302-305
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• 2000

This paper proposed an optimal register resource allocation algorithm using graph coloring for minimal register at high level synthesis. The proposed algorithm constructed interference graph consist of the intermediated representation CFG to description VHDL. and at interference graph fur the minimal select color selected a position node at stack, the next inserted spill code and the graph coloring process executes for optimal register allocation. The proposed algorithm proves to effect that result compare another allocation techniques through experiments of bench mark.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.3
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• pp.444-453
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• 1997

This paper presents the prototype design of hardware/software cosynthesis system for pipelined application-specific instruction processors. Taking application programs in VHDL as inputs, the proposed system generates a pipelined instruction-set processor and the instruction sequences running on the generated machine. The design space of datapath and controller is defined by the architectural templates embedded in the system. Generating the intyermediate code adequate for parallelism analysis and extraction, the system converts it into assembly codes. Experimental results show the effectiveness of the proposed system.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.7 no.1
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• pp.33-44
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• 1997

BISDN(Broadband Integrated Service Digital Network)의 AAL-1(ATM Adaptation Layer-1)에서는 오류정정능력이 2인 (128,124) RS(Reed Slomon) 부호를 이용하여 ATM 셀에서 발생하는 오류를 정정하고 있다. 본 논문에서는 기존의 RS 복호 알고리즘을 분석한 후, 이를 바탕으로 AAL-1 기본오류정정 모드에 적용 가능한 복잡도가 낮고 고속 동작이 가능한 복호 알고리즘을 제시하고, 부호기와 보호기를 VHDL로 부호화하고 설계한 후, 관련 회로를 시뮬레이션한다. 또한 시뮬레이션된 회로를 XACT을 이용하여 XC 4025 FPGA에 실현하여 제안되 복호 알고리즘의 타당성을 확인한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.6C
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• pp.442-449
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• 2005

In this paper, we introduce three kinds of simplified high-speed decoding algorithms for turbo product decoder. First, A parallel decoder structure, the row and column decoders operate in parallel, is proposed. Second, HAD(Hard Decision Aided) algorithm is used for early-stopping algorithm. Lastly, P-Parallel TPC decoder is a parallel decoding scheme, processing P rows and P columns in parallel instead of decoding one by one as that in the original scheme.

• Journal of Korea Society of Industrial Information Systems
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• v.11 no.4
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• pp.72-81
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• 2006

In this paper, we first define a total of 64 instructions that are considered to be essential and frequently used, construct a datapath diagram, determine the control sequence using a finite state machine, and implement an 8-bit microcontroller using FPGA in VHDL. In the past, only functional simulation results of a rudimentary microcontroller were reported, the microcontroller lacked interrupt handling capability, or it was not implemented in hardware. We have designed a self-contained 8-bit microcontroller such that it can perform data transfer, addition, and logical operations, as well as stack and external interrupt operations. Following timing simulation of the designed microcontroller, we implemented it in an FPGA and verified its operation successfully. The design and implementation has been done under the Altera MAX+PLUS II integrated development environment using the EP1K50TC144-3 chip. The maximum operating frequency, the total number of logic elements used, and the logic utilization were found to be 9.39 MHz, 2813, and 97%, respectively. The result can be used as a microcontroller IP, and as needs arise, the VHDL code can be modified accordingly.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1109-1112
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• 1998

In this paper, we propose a new architecture of the PN code acquistion system which has some shared blocks in order to reduce the hardware complexity. The proposed system has an energy calculation block which is shared by two active correlators. Our system is designed suitable for IS-95 based CDMA PCS. The new architecture was designed and simulated using VHDL. Also, We implemented it with Altera FPGA, and verified our system. The gate count is about 7,500. Our proposed architecture is also useful for multi-carrier system which uses the multiple searcher.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2000.11a
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• pp.123-134
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• 2000

In this study, adapted Turbo Coding Algorithm for reducing communication error of fire detection system for marine vessels, especially image transmission. and proposed decoding speed increasing method of Turbo Coding Algorithm. The results are as follows : 1) Confirmed that a Turbo Code is so useful methods for reducing communication error in lots of noise environments. 2) Proposed technology in this study of speed increasing method of Turbo Coding Algorithm proved 2 times speed up effect than normal Turbo Code and communication error reducing as well in the board made by VHDL software & chips of ALTER Company.

• Journal of Advanced Navigation Technology
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• v.15 no.2
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• pp.298-306
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• 2011

In this paper, the RUNCODE encoder hardware IP was designed and implemented for symbol ID code length encoding, which is one of major modules of JBIG2 encoder for FAX. ImpulseC Codeveloper and Xilinx ISE/EDK program are used for the hardware generation and synthesis of VHDL code. The synthesized hardware was downloaded to Virtex-4 FX60 FPGA on ML410 development board. The synthesized hardware utilizes 13% of total slice of FPGA. Using Active-HDL tool, the hardware was verified showing normal operation. Compared with the software operating using Microblaze cpu on ML410 board, the synthesized hardware was better in operation time. The improvement ratio of operation time between the synthesized hardware and software showed about 40 times faster than software only operation. The synthesized H/W and S/W module cooperated to succeed in compressing the CCITT standard document.