• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.5
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• pp.468-474
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• 2010

In this paper, a VCHO(Voltage Controlled Harmonic Oscillator) for K-band application has been designed and implemented. The proposed oscillator has a structure of two hair-pin resonators placed on input and output of active device. Using in/out common frequency tuning structure, the VCHO yields some advantages of the enhanced fundamental frequency suppression characteristic as well as the improved output power of second harmonic. According to implementation and measurement results, it was shown that a VCHO provides an output power of -2.41 dBm, a fundamental frequency suppression of -21.84 dBc, and phase noise of -101.44 dBc/Hz at 100 kHz offset. In addition, as for the bias voltage from 0 V to -10 V for the varactor diode, output frequency range of 10.58 MHz is obtained with a power variation of ${\pm}0.19\;dB$ over its frequency range.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.963-972
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• 2002

An 8192-point pipelined FFT/IFFT processor core is designed, which can be used in multi-carrier modulation systems such as DUf-based VDSL modem and OFDM-based DVB system. In order to improve the signal-to-quantization-noise ratio (SQNR) of FFT/IFFT results, two-step convergent block floating-point (TS_CBFP) scaling is employed. Since the proposed TS_CBFP scaling does not require additional buffer memory, it reduces memory as much as about 80% when compared with conventional CBFP methods, resulting in area-and power-efficient implementation. The SQNR of about 60-㏈ is achieved with 10-bit input, 14-bit internal data and twiddle factors, and 16-bit output. The core synthesized using 0.25-$\mu\textrm{m}$ CMOS library has about 76,300 gates, 390K bits RAM, and twiddle factor ROM of 39K bits. Simulation results show that it can safely operate up to 50-㎒ clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. It was verified by Xilinx FPGA implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.4
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• pp.1068-1076
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• 1996

In this paper, a new continuous-time current-mode integrator as basic building block of the low-voltage analyog current-mode active filters is proposed. Compared to the current-mode integrator which is proposed by Zele, the proposed current-mode integrator had higher unity gain frequency and output impedance in addition to lower power dissipation. And also, a current-mode third-order lowpass active filter is designed with the proposed current-mode integrator. The designed circuits are fabricated using the ORBIT's $1.2{\mu}{\textrm{m}}$ deouble-poly double-metal CMOS n-well process. The experimental results show that the filter has -3dB cutoff frequency at 44.5MHz and 3mW power dissipation with single 3.3V power supply and also $0.12mm^{2}$ chip area.

• Korean Journal of Optics and Photonics
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• v.26 no.5
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• pp.269-274
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• 2015

In this paper we design the optical system for an integrated two-channel TO-type optical transmitter to apply the HDMI interface using the code V simulator. The proposed integrated two-channel optical transmitter has two VCSELs attached in parallel on an 8-pin TO-CAN package, on top of which is a lens filter block ($1mm{\times}2mm{\times}4mm$) composed of hemispherical lenses and WDM filters. Considering two-channel transmitters manufactured with wavelength combinations of 1060nm/1270nm and 1330nm/1550nm, we obtain the optimum value of the diameter of the hemispherical lens as 0.6 mm for both combinations, and the distances L between the lens filter block and ball lens as 1.7 mm and 2.0 mm for the 1060nm/1270nm and 1330nm/1550nm wavelength combinations, respectively. At this time, the focal length f0 of the lens filter blocks for wavelengths of 1060, 1270, 1330, and 1550 nm are 0.351, 0.354, 0.355, and 0.359 mm, respectively, and the focal lengths F of light passing through the lens filter block and ball lens are 0.62 mm for 1060nm/1270nm and 0.60-0.66 mm for 1330nm/1550nm wavelength combinations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.101-111
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• 2008

This paper introduces a high-speed Reed-Solomon(RS) decoder, which reduces the hardware complexity, and presents an RS decoder based FEC architecture which is used for 40Gb/s optical communication systems. We introduce new pipelined degree computationless modified Euclidean(pDCME) algorithm architecture, which has high throughput and low hardware complexity. The proposed 16 channel RS FEC architecture has two 8 channel RS FEC architectures, which has 8 syndrome computation block and shared single KES block. It can reduce the hardware complexity about 30% compared to the conventional 16 channel 3-parallel FEC architecture, which is 4 syndrome computation block and shared single KES block. The proposed RS FEC architecture has been designed and implemented with the $0.18-{\mu}m$ CMOS technology in a supply voltage of 1.8 V. The result show that total number of gate is 250K and it has a data processing rate of 5.1Gb/s at a clock frequency of 400MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.3
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• pp.685-690
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• 2013

This paper has proposed a multi-channel and wide gain-range baseband circuit blocks for the IEEE 802.15.4g MR-OFDM SUN systems. The proposed baseband circuit blocks consist of two negative-feedback VGAs, an active-RC 5th-order chebyshev low-pass-filter, and a DC-offset cancellation circuit. The proposed baseband circuit blocks provide 1 dB cut-off frequencies of 100 kHz, 200 kHz, 400 kHz, and 600 kHz respectively, and achieve a wide gain-range of +7 dB~+84 dB with 1 dB step. In addition, a DC-offset cancellation circuit has been adopted to mitigate DC-offset problems in direct-conversion receiver. Simulation results show a maximum input differential voltage of $1.5V_{pp}$ and noise figure of 42 dB and 37.6 dB at 5 kHz and 500 kHz, respectively. The proposed I-and Q-path baseband circuits have been implemented in $0.18-{\mu}m$ CMOS technology and consume 17 mW from a 1.8 V supply voltage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.349-351
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• 2013

This research paper presents a low-power programmable gain amplifier (PGA) to facilitate signal processing of the detection of defects in steel plates. This circuit is able to adjust a gain in the range of 6 to 60dB in 7 steps using different signal types for various defects from hall sensors. The gain of PGA is designed by operating on-resistors of switches and passive components. The proposed PGA ($0.18{\mu}m$ CMOS process with 1.8 supply voltage) showed excellent gain error of less than -0.2dB, and low power consumption of 0.47mW.

• ETRI Journal
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• v.29 no.4
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• pp.437-444
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• 2007

A CMOS frequency synthesizer block for multi-band orthogonal frequency division multiplexing ultra-wideband systems is proposed. The proposed frequency synthesizer adopts a double-conversion architecture for simplicity and to mitigate spur suppression requirements for out-of-band interferers in 2.4 and 5 GHz bands. Moreover, the frequency synthesizer can consist of the fewest nonlinear components, such as divide-by-Ns and a mixer with the proposed frequency plan, leading to the generation of less spurs. To evaluate the feasibility of the proposed idea, the frequency synthesizer block is implemented in 0.18-${\mu}m$ CMOS technology. The measured sideband suppression ratio is about 32 dBc, and the phase noise is -105 dBc/Hz at an offset of 1 MHz. The fabricated chip consumes 17.6 mA from a 1.8 V supply, and the die-area including pads is $0.9{\times}1.1\;mm^2$.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.3
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• pp.260-264
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• 2008

In this paper, a dual mode baseband analog channel selection filter is described which is designed for the Bluetooth and WCDMA wireless communications. Using the presented current-mode integrator, a dual mode channel selection filter is designed. To verify the current-mode integrator circuit, Hspice simulation using 1.8V Hynix $0.18{\mu}m$ standard CMOS technology was performed and achieved $50.0{\sim}4.3dB$ gain, $2.29{\sim}10.3MHz$ unity gain frequency. The described third-order dual mode analog channel selection filter is composed of the current-mode integrator, and used SFG(Signal Flow Graph) method. The simulated results show 0.51, 2.40MHz cutoff frequency which is suitable for the Bluetooth and WCDMA baseband block each.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.12
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• pp.1851-1857
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• 2016

Existing devices are capable of communicating the OBD information only inside or close to the vehicle without supporting the data transmission to a external server. In this paper, we describe the implementation of IoT device, which can communicate the OBD information to the external server.