• Information and Communications Magazine
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• v.12 no.1
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• pp.59-69
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• 1995

이동통신에 대한 수요가 급증하고 있는 이즈음 Battery의 효율적인 사용이 휴대 전화기에 있어서 중요한 문제점으로 부각되고 있다. 본 논문은 LTI에서 1991년 후반부터 개발을 시작 1992년에 개발완료한 아날로그 방식의 5.8V 휴대전화기용 고주파전력 증폭기에 관한 것으로 이것의 일반적인 설계 방법과, 시험 및 생산 방법을 기술하고자 한다. 이와 같이 설계된 고주파 전력증폭기는 양산성이 있으며, 효율 60% typ. 출력 31.5dBm 이상 그리고 2차 3차, 및 4차 고조파가 모두 30 dBc 미만이며 그 외에 load missmatch, Noise, Spurious 특성이 휴대전화기에 적용하기 알맞게 안전하도록 설계되어 있다. 또한 장착의 효율성을 위해 크기를 최소화하여 1.4cc의 체적을 갖고 있다.

• Communications of the Korean Mathematical Society
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• v.34 no.2
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• pp.585-602
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• 2019

We characterize Gelfand-continuous functions from a Tychonoff space X into an Arens-Michael algebra A. Then we define several algebras of such functions, and investigate them as topological algebras. Finally, we provide a class of examples of (metrizable) commutative unital complete Arens-Michael algebras A and locally compact spaces X for which all these algebras differ from each other.

• Communications of the Korean Mathematical Society
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• v.36 no.2
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• pp.389-400
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• 2021

For a graph G, the variable sum exdeg index SEI_a(G) is defined as Σ_u∈V(G)d_G(u)a^d_G(u), where a ∈ (0, 1) ∪ (1, +∞). In this work, we determine the minimum and maximum variable sum exdeg indices (for a > 1) of n-vertex cactus graphs with k cycles or p pendant vertices. Furthermore, the corresponding extremal cactus graphs are characterized.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.100-105
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• 2010

A multi-band low noise amplifier (LNA) is designed in 90 nm RF CMOS process for 3GPP LTE (3rd Generation Partner Project Long Term Evolution) applications. The designed multi-band LNA covers the eight frequency bands between 1.85 and 2.8 GHz. A tunable input matching circuit is realized by adopting a switched capacitor array at the LNA input stage for providing optimum performances across the wide operating band. Current steering technique is adopted for the gain control in three steps. The performances of the LNA are verified through post-layout simulations (PLS). The LNA consumes 17 mA at 1.2 V supply voltage. It shows a power gain of 26 at the normal gain mode, and provides much lower gains of 0 and -6.7 in the bypass-I and -II modes, respectively. It achieves a noise figure of 1.78 dB and a IIP3 of -12.8 dBm over the entire band.

• The Bulletin of The Korean Astronomical Society
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• v.36 no.2
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• pp.82.2-82.2
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• 2011

Major solar eruptive events, consisting of both a large flare and a near simultaneous fast coronal mass ejection (CME), are the most powerful explosions in the solar system, releasing $10^{32}-10^{33}$ ergs in ${\sim}10^{3-4}\;s$. They are also the most powerful and energetic particle accelerators, producing ions up to tens of GeV and electrons up to hundreds of MeV. For flares, the accelerated particles often contain up to ~50% of the total energy released, a remarkable efficiency that indicates the particle acceleration is intimately related to the energy release process. Similar transient energy release/particle acceleration processes appear to occur elsewhere in the universe, in stellar flares, magnetars, etc. Escaping solar energetic particles (SEPs) appear to be accelerated by the shock wave driven by the fast CME at altitudes of ~1 40 $R_s$, with an efficiency of ~10%, about what is required for supernova shock waves to produce galactic cosmic rays. Thus, large solar eruptive events are our most accessible laboratory for understanding the fundamental physics of transient energy release and particle acceleration in cosmic magnetized plasmas. They also produce the most extreme space weather - the escaping SEPs are a major radiation hazard for spacecraft and humans in space, the intense flare photon emissions disrupt GPS and communications on the Earth, while the fast CME restructures the interplanetary medium with severe effects on the magnetospheres and atmospheres of the Earth and other planets. Here I review present observations of large solar eruptive events, and future space and ground-based measurements needed to understand the fundamental processes involved.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11A
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• pp.1848-1857
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• 2001

This paper proposes the ETEO and MTEO burst signal detector based on TEO algorithm. These algorithms must be used after STR and AGC operation, but are not related to phase and frequency offset. ETEO algorithm is extended version of original TEO, and MTEO algorithm is proposed for improving the output characteristics of ETEO. Also, modified ETEO and MTEO algorithm are proposed for detection of PREAMBLE64. Optimal threshold value is determined and miss and false alarm probability and FER performance are evaluated by computer simulation. Finally, this paper proposes MTEO algorithm with M=3 to guarantee the Performance that FER is less than 10$\^$-2/.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2008.04a
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• pp.243-246
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• 2008

ISM(Industrial, Scientific, Medical)대역은 비면허 대역으로 일정한 출력 규제만 지키면 자유롭게 사용할 수 있다는 장점으로 인하여 육상 통신뿐만 아니라 해상 통신 영역까지 그 사용량이 급증하고 있다. 이에 어선 내에서 사용하는 전파응용설비 및 ISM대역을 사용하는 소출력무선기기 등과의 전파간섭 문제는 시스템의 안정성을 열화시킬 수 있는 요인이 되며, 선박상황을 고려하면 안전성과 직결되므로, 간과되지 말아야 한다. 따라서 ISM대역에서 사용되거나 사용될 무선설비의 간섭확률 분석은 필수적이다. 본 논문에서는 Monte-Carlo 방식을 기반으로 하는 SEAMCAT를 이용하여 거리 및 밀도에 따른 간섭 시나리오와 전파 간섭 simulation methodology를 제안하였으며, 해상에서 환경을 가정하여 다른 전파간섭을 배제하였다. 제안된 시나리오를 적용하여 13.56MHz ISM 대역의 거리 시나리오 시뮬레이션 결과 RFID는 4.7m 이상, 모형기기는 2.7m 이상의 동종 기기간 이격거리를 가질 경우 간섭 영향이 양호하였다. 밀도 시나리오 시뮬레이션 결과 RFID(${V_r}$)를 중심으로 간섭 영향권에 RFID와 모형기기가 각각 2개 이하, 모형기기(${V_r}$)를 중심으로 간섭 영향권에 모형기기 2개 이하, RFID 1개 이하로 사용될 경우 통신환경이 양호함을 알 수 있었다. 제안된 간섭 시나리오 및 시뮬레이션 기법은 향후 ISM대역의 규제 정책 및 간섭확률 분석에 기여할 것으로 기대된다.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2024-2034
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• 2016

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.

• Journal of Power Electronics
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• v.17 no.3
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• pp.821-834
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• 2017

This paper reports on a single-inductor multiple-output step-up converter with digital control. A systematic analog-to-digital-controller design is explained. The number of digital blocks in the feedback path of the proposed converter has been decreased. The simpler digital pulse-width modulation (DPWM) architecture is then utilized to reduce the power consumption. This architecture has several advantages because counters and a complex digital design are not required. An initially designed unit-delay cell is adopted recursively for the construction of coarse, intermediate, and fine delay blocks. A digital limiter is then designed to allow only useful code for the DPWM. The input voltage is 1.8 V, whereas output voltages are 2 V and 2.2 V. A co-simulation was also conducted utilizing PowerSim and Matlab/Simulink, whereby the 55 nm process was employed in the experimental results to evaluate the performance of the architecture.

• ETRI Journal
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• v.30 no.1
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• pp.33-46
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• 2008

This paper presents the experimental results of a low-power low-cost RF transceiver for the 915 MHz band IEEE 802.15.4b standard. Low power and low cost are achieved by optimizing the transceiver architecture and circuit design techniques. The proposed transceiver shares the analog baseband section for both receive and transmit modes to reduce the silicon area. The RF transceiver consumes 11.2 mA in receive mode and 22.5 mA in transmit mode under a supply voltage of 1.8 V, in which 5 mA of quadrature voltage controlled oscillator is included. The proposed transceiver is implemented in a 0.18 ${\mu}m$ CMOS process and occupies 10 $mm^2$ of silicon area.