• Journal of applied mathematics & informatics
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• v.39 no.5_6
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• pp.689-701
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• 2021

The purpose of this paper is to optimize the number of source places required for the unique representation of the destination using the tools of graph theory. A subset S of vertices of a graph G is called a rational resolving set of G if for each pair u, v ∈ V - S, there is a vertex s ∈ S such that d(u/s) ≠ d(v/s), where d(x/s) denotes the mean of the distances from the vertex s to all those y ∈ N[x]. A rational resolving set is called minimal rational resolving set if no proper subset of it is a rational resolving set. In this paper we study varieties of minimal rational resolving sets defined on the basis of its complements and compute the minimum and maximum cardinality of such sets, respectively called as lower and upper rational metric dimensions for power of a path P_n analysing various possibilities.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.19-27
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• 2007

This paper presents power supply-insensitive Gbps low power LVDS I/O circuits. The proposed LVDS I/O has been designed and simulated using 1.8V, $0.18\;{\mu}m$ TSMC CMOS Process. The LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and an output stage with the switched capacitor common mode feedback(SC-CMFB). The differential phase splitter generates a pair of differential signals which provides a balanced duty $cycle(50{\pm}2%)$ and phase difference$(180{\pm}0.2^{\circ})$ over a wide supply voltage range. Also, $V_{OD}$ voltage is 250 mV which is the smallest value of the permissible $V_{OD}$ range for low power operation. The output buffer maintains the required $V_{CM}$ within the permissible range$(1.2{\pm}0.1V)$ due to the SC-CMFB. The receiver covers a wide input DC offset $range(0.2{\sim}2.6\;V)$ with 38 mV hysteresis and Produces a rail-to-rail output over a wide supply voltage range. Beside, the designed receiver has 38.9 dB gain at 1 GHz, which is higher than conventional receivers.

• Journal of Convergence for Information Technology
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• v.11 no.7
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• pp.104-110
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• 2021

A novel selective oxidation process has been developed for low source/drain (S/D) series resistance of the fin channel metal oxide semiconductor field effect transistor (MOSFET). Using this technique, the selective oxidation fin-channel MOSFET (SoxFET) has the gate-all-around structure and gradually enhanced S/D extension regions. The SoxFET demonstrated over 70% reduction in S/D series resistance compared to the control device. Moreover, it was found that the SoxFET behaved better in performance, not only a higher drive current but also higher transconductances with suppressing subthreshold swing and drain induced barrier lowering (DIBL) characteristics, than the control device. The saturation current, threshold voltage, peak linear transconductance, peak saturation transconductance, subthreshold swing, and DIBL for the fabricated SoxFET are 305 ㎂/㎛, 0.33 V, 13.5 𝜇S, 76.4 𝜇S, 78 mV/dec, and 62 mV/V, respectively.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.67-73
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• 2001

To investigate the relationships of solder joint characteristics with solder composition and A:V ratio (solder volume per pad area), Sn-37Pb and Sn-4.0Ag-0.5Cu solder balls with 330, 400, 450 and $457{\mu}{\textrm}{m}$ size were reflowed on same substrate. Sn-37Pb and Sn-4.0Ag-0.5Cu was reflowed at $220^{\circ}C$ and $240^{\circ}C$ respectively by IR-type soldering machine. As a result of reflowed solder- ball diameter(D) and height(H) measurement, D/H was decreased with solder ball size increment in range of 330~450 ${\mu}{\textrm}{m}$. But, D/H was increased in the solder joint for 457 ${\mu}{\textrm}{m}$ size, it was caused possibly by decrement of solder ball height increment compared with solder volume increment. As a result of shear and pull test, joint strength with A:V ratio was high. Joint strength of Sn-4.0Ag-0.5Cu was higher than Sn-37Pb. However, Sn-37Pb had more stable solder joint of small standard deviation. A thick and clean scallop type Ni-Cu-Sn intermetallic compound layer was formed in high A:V ratio and Sn-4.0Ag-0.5Cu solder joint interface.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.35-42
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• 2010

This paper describes a 10 bit 80MHz CMOS D/A converter for wireless communication system. The proposed circuit in the paper is implemented with a $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process. The architecture of the circuit consists of the 4bit LSB with binary decoder, and both the 3bit ULSB and the 3bit MSB with the thermometer decoder. The measurement results demonstrates SFDR of 60.42dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB of 8.75bit. INL and DNL have been measured to be ${\pm}$0.38LSB and ${\pm}$0.32LSB and glitch energy is measured to be 4.6$pV{\cdot}s$. Total power dissipation is 48mW at 80MHz(maximum sampling frequency) with a single power supply of 1.8V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.187-191
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• 2007

This paper describes a 3.3V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method with monotonicity, glitch energy. The output stage utilizes here implements a return-to-zero circuit to obtain the dynamic performance. Most of D/A converters in decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. the designed D/A converter using the CMOS n-well $0.35{\mu}m$ process0. The experimental data shows that the rise/fall time, settling time, and INL/DNL are 1.90ns/2.0ns, 12.79ns, and a less than ${\pm}2.5/{\pm}0.7$ LSB, respectively. The power dissipation of the D/A converter with a single power supply of 3.3V is about 250mW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.4
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• pp.691-698
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• 2008

This paper describes a 3.3V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method with monotonicity, glitch energy. The output stage utilizes here implements a return-to-zero circuit to obtain the dynamic performance. Most of D/A converters in decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. the designed D/A converter using the CMOS n-well $0.35{\mu}m$ process0. The experimental data shows that the rise/fall time, settling time, and INL/DNL are 1.90ns/2.0ns, 12.79ns, and a less than ${\pm}2.5/{\pm}0.7\;LSB$, respectively. The power dissipation of the D/A converter with a single power supply of 3.3V is about 250mW.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.88-97
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• 1994

We describe the design, fabrication, and performance of the optical fiber-photodiode 1$\times$12 arry module using mesa-type InS10.53T GaS10.47TAS/INP 1$\times$12 PIN photodiode array. We fabricated the PIN PD array for high-speed optical fiber parallel data link optimizing quantum efficiency, operating speed sensitivity from the PIN-FET structure, and electrical AC crosstalk. For each element of the array, the diameter of the photodetective area is 80 $\mu$m, the diameter of the p-metal pad is 90 $\mu$m, and the photodiode seperation is 250 $\mu$m to use Si v-groove. Ground conductor line is placed around diodes and p-metal pads are formed in zigzag to reduce Ac capacitance coupling between array elements. The dark current (IS1dT) is I nA and the capacitance(CS1pDT) is 0.9 pF at -5 V. No signifcant variations of IS1dT and CPD from element to element in the array were observed. We calulated the coupling efficiency for 10/125 SMF and 50/125 GI MMF, and measured the responsivity of the PD array at the wavelength is 1.55 $\mu$ m. Responsivities are 0.93 A/W for SMF and 0.96 A/W for MMF. The optical fiber-PD array module is useful in numerous high speed digital and analog photonic system applications.

• Nuclear Engineering and Technology
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• v.18 no.2
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• pp.92-96
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• 1986

The $^{93}Nb(n,n\alpha)^{89m}Y$, $^{93}Nb(n,{\alpha})^{90m}Y$ and $^{93}Nb(n,2n)^{92m}Nb$ cross sections at a neutron energy of 14.6 MeV have been measured relative to the $^{27}Al(n,p)^{27}Mg$ and $^{27}Al(n,{\alpha})^{24}Na$ cross sections. A small accelerator utilizing $T(D,n)^4He$ reaction was used as a neutron source and the neutron energy spread is about 0.4MeV at the sample. All induced activities were measured with a 70cc HPGe detector in the same geometry.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.9
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• pp.820-825
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• 2004

In this paper an octave tuning voltage controlled oscillator which is used in set-top TV tuner was designed. Oscillation frequency range is 0.9 GHz～2.2 GHz with 1.3 GHz bandwidth. By using 4 varactor diodes in base and emitter of transistor, wide-band tuning, sweep linearity and low phase noise could be achieved. Designed VCO requires a tuning voltage of 0 V ～ 20 V and DC consumption of 10 V and 15 mA. Designed VCO exhibits an output power of 5.3 dBm $\pm$1.1 dB and a phase noise below -94.8 dBc/Hz ＠ 10 kHz over the entire frequency range. The sweep linearity shows 65 MHz/V with a deviation of $\pm$10 MHz.