• Proceedings of the PSK Conference
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• 2000.10a
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• pp.128.2-128.2
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• 2000

• Progress in Superconductivity and Cryogenics
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• v.20 no.1
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• pp.11-14
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• 2018

High Temperature Superconducting (HTS) power cables are capable of transmitting bulk power without any loss compared to conventional copper cables. The major challenge in the design of such HTS cables is the high stresses (electro-thermal/electro-mechanical) developed at high voltages, high currents and cryogenic temperatures. The safe and reliable operation of HTS cables involves lots of instrumentation for monitoring, measurement, control and safe operation. In principle, a four probe method for resistance (RTD PT-100) is used for temperature measurements at various locations of HTS cable. The number of connecting leads required for this is four times that of the number of sensors. The present paper discusses a novel way of connecting 128 RTD sensors with the help of only 14 leads using a cold electronics based multiplexer board. LabVIEW 11.0 software was used for interfacing and displaying the readings of all the sensors on computer screen.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.2 no.1
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• pp.30-36
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• 1992

In order to measure the characteristics of Surface Acousitc Wave(SA W) with compositions of $LiNbO_3$ single crystal, $128^{\circ}$ Y cut wafer was fabricated from $LiNbO_3$ single crystals with the composition range of 47-50 $Li_2O$mol%. Delay lines were formed on the $128^{\circ}$ Y cut wafer using photolithography technique. Delay time was measured by pulse-echo overlap method. The compositional dependence of SAW characteristics, SAW velocity, electro-mechanical coupling coefficient$(K_s^2)$ and temperature coefficient of delay time(TCD), were investigated.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.17 no.2
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• pp.128-141
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• 2018

In this paper, a methodology to analyze the potential safe benefit of six cooperative driver assistance systems via V2V (vehicle-to-vehicle) communications is proposed. Although it is quite necessary to assess social impact with respect to new safety technologies for cooperative vehicles with V2V communications, there are few studies in Korea to predict the quantitative safety benefit analysis. In this study, traffic accident scenarios are classified based on traffic fatality between passenger cars. The sequential collision type is classified for a multiple pile-up with respect to collision direction such as forward, side, head-on collisions. Then movement of surrounding vehicle is considered for the scenario classification. Next, the cooperative driver assistance systems such as forward collision warning, blind spot detection, and intersection movement assistance are related with the corresponding accident scenarios. Finally, it is summarized how much traffic fatality may be reduced potentially due to the V2V communication based safety services.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.4
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• pp.1059-1067
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• 1996

A 128/129 dual-modulus prescalar IC is designed for application to frequency synthesizers in high frequency communication systems. The FET logic used in this design is SCFL(Source Coupled FET Logic), employing depletion-mode 1.mu.m gate length GaAs MESFETs with the threshold voltage of -1.5V. This circuit consists of 8 flip-flops, 3 OR gates, 2 NOR gates, a modulus control buffer and I/O buffers, which are integrated with about 440 GaAs MESFETs on dimensions of 1.8mm. For $V_{DD}$ and $V_{SS}$ power supply voltages 5V and -3.3V Commonly used in TTL and ECL circuits are determined, respectively. The simulation results taking into account the threshold voltage variation of .+-.0.2V and the power supply variation of .+-.1V demonstrate that the designed prescalar can operate up to 2GHz. This prescalar is fabricated using the ETRI MMIC foundary process and the measured maximum operating frquency is 621MHz.

• Korean Journal of Environmental Agriculture
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• v.22 no.1
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• pp.60-64
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• 2003

This study was conducted to examine the effects of plug tray cell size and growth media on good seedling production of Gerbera hybrida Hort. Seedlings were grown for 60 days in 50, 72, 128, 162 cell trays contanning perlite, cocopeat and perlite+cocopeat(1:1, v/v). Perlite showed higher bulk density than cocopeat and perlite+cocopeat. Total porosity was greater in perlite, cocopeat and perlite+cocopeat in order. Cocopeat showed the highest water holding capacity. Number of leaves were greatest in 128 cell tray containing cocopeat. Leaf area was greatest in 50 cell tray containing cocopeat. Seedling growth was also better in plug tray of bigger cell size. Seedling growth of fresh and dry weight of shoot and root was much better in the growth media of perlite+cocopeat.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.53-60
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• 2009

A low-power/small-area 128-point FFT processor is designed, which is based on logarithmic number system (LNS) and some design techniques to minimize both hardware complexity and arithmetic error. The complex-number multiplications and additions/subtractions for FFT computation are implemented with LNS adders and look-up table (LUT) rather than using conventional two's complement multipliers and adders. Our design reduces the gate counts by 21% and the memory size by 16% when compared to the conventional two's complement implementation. Also, the estimated power consumption is reduced by about 18%. The LNS-based FFT processor synthesized with 0.35 ${\mu}m$ CMOS standard cell library has 39,910 gates and 2,880 bits memory. It can compute a 128-point FIT in 2.13 ${\mu}s$ with 60 MHz@2.5V, and has the average SQNR of 40.7 dB.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.257-260
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm“Rijndael”. To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation the round transformation block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.33-43
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into a round transformation block, resulting that two consecutive round functions are simultaneously operated. For area-efficient and low-power implementation, the round transformation block is designed to share the hardware resources for encryption and decryption. An efficient on-the-fly key scheduler is devised to supports the three master-key lengths of 128-b/192-b/256-b, and it generates round keys in the first sub-pipeline stage of each round processing. The Verilog-HDL model of the cryptoprocessor was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}m$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.5
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• pp.15-25
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• 2002

In this paper a design of high performance cryptographic processor which implements AES Rijndael algorithm is described. To eliminate performance degradation due to round-key computation delay of conventional processor, the on-the-fly precomputation of round key based on modified round structure is adopted. And on-the-fly round key generator which supports 128, 192, and 256-bit key has modular structure. The designed processor has iterative structure which uses 1 clock cycle per round and supports three operation modes, such as ECB, CBC, and CTR mode which is a candidate for new AES modes of operation. The cryptographic processor designed in Verilog-HDL and synthesized using 0.251$\mu\textrm{m}$ CMOS cell library consists of about 51,000 gates. Simulation results show that the critical path delay is about 7.5ns and it can operate up to 125Mhz clock frequency at 2.5V supply. Its peak performance is about 1.45Gbps encryption or decryption rate under 128-bit key ECB mode.