• 반도체디스플레이기술학회지
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• 제18권4호
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• pp.1-5
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• 2019

This study has been focused on properties of surface technology for large diameter upper electrode using in high density plasma process as like semi-conductor manufacturing process. The experimental studies have been carried out to get mirror surface for upper electrode. For a formation of high surface quality upper electrode, single crystal silicon upper electrode has been mechanical and chemical machining worked. Mechanical machining work of the upper electrode is carried out with varying mesh type using diamond wheel. In case of chemical machining work, upper electrode surface roughness was observed to be strongly dependent upon the etchant. The different surface roughness characteristics were observed according to etchant. The machining result of the surface roughness and surface morphology have been analyzed by use of surface roughness tester, laser microscope and ICP-MS.

• 한국진공학회지
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• 제20권5호
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• pp.322-326
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• 2011

상부 전극에 RF power 가 직접 인가되는 capacitively coupled plasma source를 이용한 oxide layer etching 공정은 현재 반도체 제조 공정에서 매우 유용하게 사용되고 있는 방식이다. 그러나 디바이스의 사이즈가 점점 작아지면서 공정을 진행하기 위한 RF power도 커지고, plasma ignition 되는 electrode 사이의 간격도 점점 좁아지는 기술적 변화가 이루어지고 있다. 이러한 H/W의 변화에 따라 예상치 못한 문제들로 공정을 적용하는데 많은 문제점이 발생하고 있는데, 공정 진행 시에 plasma의 영향으로 인한 electrode의 온도 변화도 그 중 하나이다. 이러한 온도 변화로 인해 wafer to wafer의 공정 진행 결과가 서로 다르게 나타나게 하는 문제가 야기되고 있다. 아래의 내용에서는 상부 electrode의 온도 변화에 따른 etch 특성을 연구하고, 이를 개선할 수 있는 방법에 대해 논하고자 한다.

• 한국재료학회지
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• 제9권10호
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• pp.1032-1036
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• 1999

Pb($\textrm{Zr}_{0.5}\textrm{Ti}_{0.5}$)$\textrm{O}_3$ 강유전체의 상부 전극 크기를 변화시키며 펄스 전기장에 의한 전자 방출 특성 및 열화에 대하여 연구하였다. 상부 전극 크기 감소에 따라 상부 전극 모서리 부근에서 분극 반전에 기여하는 강유전체 분율이 증가되어 분극이 높아졌으며, ANSYS 5.3에 의한 전기장 시뮬레이션을 통하여 비대칭 전극 구조에서의 상부 전극 모서리 부근의 전기장이 증가한다는 것을 알 수 있었다. 분극 증가에 기여하는 상부 전극 모서리 주변의 강유전체의 부피 및 전극크기당 전자 방출량은 상부 전극 크기에 무관하였다. 전자 방출 횟수에 따라 상부 전극이 침식되어 분극 및 유전 상수는 감소하였으나 전극 복구에 의해 재생되었으며, 강유전체의 표면 손상에 의해 항전계 및 유전 손실은 증가되었다.

• 한국전기전자재료학회논문지
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• 제24권3호
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• pp.224-228
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• 2011

This research, integratable capacitive relative humidity sensor was produced using polyimide on glass substrate. Also, at the time of upper electrode formation, upper electrode grain size was affected by giving changes to sputtering condition. Through this analyzing electrical characteristics affect from capacitive relative humidity sensor was possible. Capacitance of capacitive relative humidity sensor was 330 pF, linearity of 0.6%FS and it showed less than 3% of low hysterisis. Specially, hysterisis was affected more from interface than interstitial. Also was affected by the grain size which is one of the formation condition of upper electrode.

• 반도체디스플레이기술학회지
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• 제20권1호
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• pp.59-63
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• 2021

Upper electrode is one of core parts using plasma etching process at semiconductor. The purpose of this study is to analyze effects of cutting conditions for mechanical machining of silicon upper electrode. For this research, surface roughness of machined workpiece and depth of damage inside of silicon electrode are experimented and analyzed and different values of feed rate and depth of cut are applied for the experiments. From these experiments, it is verified that the surface roughness and internal damaged layer get worse according to take more fast feed rate. In conclusion, cutting condition is very important factor for machining. Results of this study can use to develop various parts which are made from single crystal silicon and affect various benefits to the semiconductor industry for better productivity.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권1호
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• pp.30-37
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• 2005

We present an air bridge type electrode system with tunable electrode distance for detecting electroactive biomolecules. It is known that the narrower gap between electrode fingers, the higher sensitivity in IDA (interdigitated array) electrode. In previous researches on IDA electrode, narrower patterning required much precise and expensive equipment as the gap goes down to nanometer scale. In this paper, an improved method is suggested to replace nano gap pattering with downsizing electrode distance and showed that the patterning can be replaced by thickness control using metal deposition methods, such as electroplating or metal sputtering. The air bridge type electrode was completed by the following procedures: gold patterning for lower electrode, copper electroplating, gold deposition for upper electrode, photoresist patterning for gold film support, and copper etching for space formation. The thickness of copper electroplating is the distance between upper and lower electrodes. Because the growth rate of electroplating is $0.5{\mu}m\;min^{-1}$, the distance is tunable up to hundreds of nanometers. Completed electrodes on the same wafer had $5{\mu}m$ electrode distance. The gaps between fingers are 10, 20, 30, and $40{\mu}m$ and the widths of fingers are 10, 20, 30, 40, and $50{\mu}m$. The air bridge type electrode system showed better sensitivity than planar electrode.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 추계학술대회 논문집 전기물성,응용부문
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• pp.297-299
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• 2003

In this paper, we present the fabrication of copper electrode array and test of electrochemical discharge machining for the fabrication of microholes on Borofloat33 glass. Copper electrode array is fabricated by the bonding of silicon upper substrate and lower substrate and copper electroplate. The silicon upper electrode having microholes fabricated by ICP-RIE is the mold of copper electroplate. The lower substrate is used as the seed layer for copper electroplate after Au - Au thermocompression bonding with the upper substrate.

• 반도체디스플레이기술학회지
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• 제11권1호
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• pp.41-47
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• 2012

In DSSC, fundamental process conditions of upper electrode were established and low cost-oriented method for TCO layer was proposed. Especially, prominent properties, that is, open-circuit voltage of 500mV or more and short-circuit current of $25mA/cm^2$ were yielded by 2-step sintering of semiconductive powder layer. High efficiency-DSSC was able to fabricate without high cost-semiconductor apparatus in common laboratory conditions.

• 한국세라믹학회지
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• 제39권1호
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• pp.92-98
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• 2002

Pb(Zr$_{0.8}$Ti$_{0.2}$)O$_3$강유전체 음극의 상부 전극 크기를 변화시키며(500$mu extrm{m}$~900$\mu\textrm{m}$)비대칭 전극 구조에서의 전자 방출에 대하여 연구하였다. 펄스 전기장을 가했을 때 나타나는 분극 반전에 의한 전류 밀도는 상부 전극 크기를 감소시킴에 따라 증가하였다. 이것은 비대팅 전극 구조에 의해 강유전체 표면에서 stray-field가 발생하고, stray field가 전극의 모서리 부근의 강유전체 표면 하부에도 분극 반전을 발생시켰기 때문이다. 전기장 전산모사를 통하여 이러한 stay-field의 존재 가능성을 예측할 수 있었고, 분극 반전에 의한 전류 밀도 측정 결과 stray-field가 미치는 거리는 약 11-l4$\mu\textrm{m}$이었다. 전자방출의 문턱전계는 항전계 의 약 3배인 61-68kV/cm이었으며, 문턱전계가 단순히 강유전체의 항전계에 의해 결정되는 것이 아니라, 강유전 음극의 구조에 의해 결정되는 stray-field의 세기와 stray-field가 미치는 거리에 영향을 받음을 전산모사를 통해 예측할 수 있었다.

• Journal of information and communication convergence engineering
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• 제5권1호
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• pp.42-44
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• 2007

The a-Si:H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si:H TFTs is inverted staggered. The gate electrode is formed by patterning with length of $8{\mu}m{\sim}16{\mu}m$ and width of $80{\sim}200{\mu}m$ after depositing with gate electrode (Cr) $1500{\AA}$ under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these, thin films is formed with a-SiN:H ($2000{\mu}m$), a-Si:H($2000{\mu}m$) and $n^+a-Si:H$ ($500{\mu}m$). We have deposited $n^+a-Si:H$, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the $n^+a-Si:H$ layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFTs decreasing parasitic capacitance of source-drain show drain current of $8{\mu}A$ at 20 gate voltages, $I_{on}/I_{off}$ ratio of ${\sim}10^8$ and $V_{th}$ of 4 volts.