• Journal of the Semiconductor & Display Technology
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• v.18 no.4
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• pp.1-5
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• 2019

This study has been focused on properties of surface technology for large diameter upper electrode using in high density plasma process as like semi-conductor manufacturing process. The experimental studies have been carried out to get mirror surface for upper electrode. For a formation of high surface quality upper electrode, single crystal silicon upper electrode has been mechanical and chemical machining worked. Mechanical machining work of the upper electrode is carried out with varying mesh type using diamond wheel. In case of chemical machining work, upper electrode surface roughness was observed to be strongly dependent upon the etchant. The different surface roughness characteristics were observed according to etchant. The machining result of the surface roughness and surface morphology have been analyzed by use of surface roughness tester, laser microscope and ICP-MS.

• Journal of the Korean Vacuum Society
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• v.20 no.5
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• pp.322-326
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• 2011

Etch process of silicon dioxide layer by using capacitively coupled plasma (CCP) is currently being used to manufacture semiconductor devices with nano-scale feature size below 50 nm. In typical CCP plasma etcher system, plasmas are generated by applying the RF power on upper electrode and ion bombardment energy is controlled by applying RF power to the bottom electrode with the Si wafer. In this case, however, etch results often drift due to heating of the electrode during etching process. Therefore, controlling the temperature of the upper electrode is required to obtain improvement of etch repeatability. In this work, we report repeatability improvement during the silicon dioxide etching under extreme process conditions with very high RF power and close gap between upper and bottom electrodes. Under this severe etch condition, it is difficult to obtain reproducible oxide etch results due to drifts in etch rate, critical dimension, profile, and selectivity caused by unexpected problems in the upper electrode. It was found that reproducible etch results of silicon dioxide layer could be obtained by controlling temperature of the upper electrode. Methods of controlling the upper electrode and the correlation with etch repeatability will be discussed in detail.

• Korean Journal of Materials Research
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• v.9 no.10
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• pp.1032-1036
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• 1999

The electron emission and degradation of the ferroelectric Pb($\textrm{Zr}_{0.5}\textrm{Ti}_{0.5}$)$\textrm{O}_3$ ceramics by the pulse electric field have been investigated as a function of the upper electrode diameter. Polarization increased with the decrease of the upper electrode diameter due to the increase of the volume fraction participated in the polarization reversal near the electrode edge. Simulation using ANSYS 5.3 for the electric field distribution showed that the electric field increased near the upper electrode edge of the asymmetric electrode structure. The ferroelectric volume near the upper electrode edge which contributed to the increase of the polarization and the emission charge per electrode diameter were independent on the upper electrode diameter. Polarization and dielectric constant were decreased due to the erosion of the upper electrode with repeating the emission cycles, but they were recovered by the electrode regeneration. The degradation of the ferroelectric surface resulted in the increase of the coercive field and dielectric loss.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.3
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• pp.224-228
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• 2011

This research, integratable capacitive relative humidity sensor was produced using polyimide on glass substrate. Also, at the time of upper electrode formation, upper electrode grain size was affected by giving changes to sputtering condition. Through this analyzing electrical characteristics affect from capacitive relative humidity sensor was possible. Capacitance of capacitive relative humidity sensor was 330 pF, linearity of 0.6%FS and it showed less than 3% of low hysterisis. Specially, hysterisis was affected more from interface than interstitial. Also was affected by the grain size which is one of the formation condition of upper electrode.

• Journal of the Semiconductor & Display Technology
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• v.20 no.1
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• pp.59-63
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• 2021

Upper electrode is one of core parts using plasma etching process at semiconductor. The purpose of this study is to analyze effects of cutting conditions for mechanical machining of silicon upper electrode. For this research, surface roughness of machined workpiece and depth of damage inside of silicon electrode are experimented and analyzed and different values of feed rate and depth of cut are applied for the experiments. From these experiments, it is verified that the surface roughness and internal damaged layer get worse according to take more fast feed rate. In conclusion, cutting condition is very important factor for machining. Results of this study can use to develop various parts which are made from single crystal silicon and affect various benefits to the semiconductor industry for better productivity.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.1
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• pp.30-37
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• 2005

We present an air bridge type electrode system with tunable electrode distance for detecting electroactive biomolecules. It is known that the narrower gap between electrode fingers, the higher sensitivity in IDA (interdigitated array) electrode. In previous researches on IDA electrode, narrower patterning required much precise and expensive equipment as the gap goes down to nanometer scale. In this paper, an improved method is suggested to replace nano gap pattering with downsizing electrode distance and showed that the patterning can be replaced by thickness control using metal deposition methods, such as electroplating or metal sputtering. The air bridge type electrode was completed by the following procedures: gold patterning for lower electrode, copper electroplating, gold deposition for upper electrode, photoresist patterning for gold film support, and copper etching for space formation. The thickness of copper electroplating is the distance between upper and lower electrodes. Because the growth rate of electroplating is $0.5{\mu}m\;min^{-1}$, the distance is tunable up to hundreds of nanometers. Completed electrodes on the same wafer had $5{\mu}m$ electrode distance. The gaps between fingers are 10, 20, 30, and $40{\mu}m$ and the widths of fingers are 10, 20, 30, 40, and $50{\mu}m$. The air bridge type electrode system showed better sensitivity than planar electrode.

• Proceedings of the KIEE Conference
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• 2003.10a
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• pp.297-299
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• 2003

In this paper, we present the fabrication of copper electrode array and test of electrochemical discharge machining for the fabrication of microholes on Borofloat33 glass. Copper electrode array is fabricated by the bonding of silicon upper substrate and lower substrate and copper electroplate. The silicon upper electrode having microholes fabricated by ICP-RIE is the mold of copper electroplate. The lower substrate is used as the seed layer for copper electroplate after Au - Au thermocompression bonding with the upper substrate.

• Journal of the Semiconductor & Display Technology
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• v.11 no.1
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• pp.41-47
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• 2012

In DSSC, fundamental process conditions of upper electrode were established and low cost-oriented method for TCO layer was proposed. Especially, prominent properties, that is, open-circuit voltage of 500mV or more and short-circuit current of $25mA/cm^2$ were yielded by 2-step sintering of semiconductive powder layer. High efficiency-DSSC was able to fabricate without high cost-semiconductor apparatus in common laboratory conditions.

• Journal of the Korean Ceramic Society
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• v.39 no.1
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• pp.92-98
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• 2002

To investigate the electrode structural effect on the ferroelectric electron emission, the electric field distribution in a 2-dimensional structure was calculated as a function of upper electrode diameter, and the switching charge density and emission charge were measured simultaneously. The simulation of the electric field distribution showed that an asymmetric electrode structure could cause a stray field on the bare surface of the ferroelectric cathode near the edge of upper electrode. The distance of stray field from the electrode edge increased with increasing ferroelectric thickness, but it did not depend on the upper electrode diameter. The switching charge density increased more on the cathode with smaller upper electrode diameter. This was attributed to the stray field on the bare ferroelectric surface near the electrode edge, because the stray field for the asymmetric ferroelectric cathode enhanced polarization switching near the electrode edge. From the switching charge density, the distance of stray field from the electrode edge was calculated as about 11-14${\mu}{\textrm}{m}$. The threshold voltage of electron emission was 61-68 kV/cm, which was almost 3 times lager than the coercive voltage. The threshold voltage was not determined just by coercive voltage, but by strength and distance of the stray-field, which largely depended on the geometrical structure of ferroelectric cathode.

• Journal of information and communication convergence engineering
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• v.5 no.1
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• pp.42-44
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• 2007

The a-Si:H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si:H TFTs is inverted staggered. The gate electrode is formed by patterning with length of $8{\mu}m{\sim}16{\mu}m$ and width of $80{\sim}200{\mu}m$ after depositing with gate electrode (Cr) $1500{\AA}$ under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these, thin films is formed with a-SiN:H ($2000{\mu}m$), a-Si:H($2000{\mu}m$) and $n^+a-Si:H$ ($500{\mu}m$). We have deposited $n^+a-Si:H$, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the $n^+a-Si:H$ layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFTs decreasing parasitic capacitance of source-drain show drain current of $8{\mu}A$ at 20 gate voltages, $I_{on}/I_{off}$ ratio of ${\sim}10^8$ and $V_{th}$ of 4 volts.