• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.55-58
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• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1T FeFET) memory celt scheme which can select one unit memory cell and program/read it. To solve the selection problem of 1T FeEET memory cell array, the row direction common well is electrically isolated from different adjacent row direction column. So, we can control voltage of common well line. By applying bias voltage to Gate and Well, respectively, we can implant IT FeEET memory cell scheme which no interface problem and can bit operation. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

• Journal of applied mathematics & informatics
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• 제8권3호
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• pp.975-987
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• 2001

We treat the problem of variance estimation for the estimator of population total, which is derived from the calibration estimation procedure corresponding to the levels of auxiliary information under nonresponse situation. We develop the calibrated variance estimation procedure using the fact that the population total and variance as well as the sample total and variance of the auxiliary variable are known. We show that the proposed variance estimation procedure improves the $Lundst\ddot{o}rm$ and $S\ddot{a}rndal's$ (1999) procedure with respect to the variance and nonresponse bias reduction through the simulation study.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1995년도 Proceedings of the Korea Automation Control Conference, 10th (KACC); Seoul, Korea; 23-25 Oct. 1995
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• pp.110-114
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• 1995

This paper presents the on-board attitude determination algorithm for LEO (Low Earth Orbit) three-axis stabilized spacecraft. Two advanced star trackers and a three-axis Inertial Reference Unit (IRU) are assumed to be attitude sensors. The gyro in the IRU provides a direct measurement of the attitude rates. However, the attitude estimation error increases with time due to the gyro drift and noise. An update filter with measurements of star trackers and/or sun sensor is designed to update these gyro drift bias and to compensate the attitude error. Kalman Filter is adapted for the on-board update filter algorithm. Simulation results will be presented to investigate the attitude pointing performance.

• Journal of the Korean Data and Information Science Society
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• 제11권2호
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• pp.225-233
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• 2000

수명시험에서 시험에 장기간 노출된 대상 부품이나 실험 대상자의 수명은 관측되는 경우보다 관측중단이 일어나기가 쉽다. 이와 같은 경우에 임의중단모형에서 생존함수 추정량으로 흔히 이용되는 Kaplan과 Meier의 추정량은 수명분포의 오른쪽 꼬리부분에서 심각한 편의가 발생된다. 이러한 문제점에 대한 대안으로 정상적으로 관측된 최장수명보다 큰 관측중단수명이 많은 극단적인 오른쪽 관측중단모형에서 새로운 비모수적 생존함수 추정량을 제안하고 그 특성을 몬테칼로 모의실험을 통하여 기존의 추정량과 비교 분석하였다.

• 대한안전경영과학회지
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• 제11권1호
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• pp.131-136
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• 2009

The research develops the calculation steps of Z sigma level, process capability index(PCI) and process performance index(PPI) applicable to the discrete process in the service industry. The paper presents three following topics used related process indexes according to the precision and accuray in the continuous process. The contents include diverse process indexs for nonconformities by SPC attribute control charts and bias coefficient. The same technique of the nonconformites is also used in the nonconforming units. The practical examples are provided to help easier understanding for users.

• International Journal of Control, Automation, and Systems
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• 제4권3호
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• pp.351-358
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• 2006

The proposed inertial measurement unit (IMU) is composed of accelerometers only. It can determine a vehicle's position and attitude, which is the Gyro-free INS. The Gyro-free INS error is deeply affected by the sensor bias, scale factor and misalignment. However, these parameters can be obtained in the laboratory. After these misalignments are corrected, the Gyro-free strap-down INS could be more accurate. This paper presents a compensator design for the strap-down six-accelerometer INS to correct misalignment. A calibration experiment is taken to get the error parameters. A simulation results show that it will decrease the INS error to enhance the performance after compensation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.403-405
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• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1Tr FeFET) memory cell scheme, which select one unit memory cell and program/read it. The well voltage can be controlled by isolating the common row well lines. Through applying bias voltage to Gate and Well, respectively, we implement If FeFET memory cell scheme in which interference problem is not generated and the selection of each memory cell is possible. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

• Journal of electromagnetic engineering and science
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• 제13권4호
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• pp.245-250
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• 2013

This paper presents a tunable bandpass filter based on the varactor-loaded composite right- and left-handed transmission line (CRLH-TL). The proposed filter is composed of one CRLH-TL unit cell, which corresponds to the third-order bandpass filter. The tunable bandpass filter is designed using only lumped-elements. The use of lumped elements saves space and lowers the fabrication cost. The size of the proposed tunable bandpass filter is $17mm{\times}5mm$, neglecting the feed lines and DC lines. All of the varactors are controlled by one DC bias. The center frequency of the bandpass filter can be controlled by varying the value of the varactors. The tunable range of the center frequency is from 412.5 to 670 MHz. The insertion loss is less than 3 dB, the return loss is more than 10 dB in the passband.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2003년도 추계학술대회 논문집
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• pp.76-78
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• 2003

We have designed and tested an RSFQ (Rapid Single Flux Quantum) NDRO (Non Destructive Read Out) circuit for the development of a high speed superconducting ALU (Arithmetic Logic Unit). When designing the NDRO circuit, we used Julia, XIC and Lmeter for the circuit simulations and layouts. We obtained the simulation margins of larger than $\pm$25％. For the tests of NDRO operations, we attached the three DC/SFQ circuits and two SFQ/DC circuits to the NDRO circuit. In tests, we used an input frequency of 1 KHz to generate SFQ Pulses from DC/SFQ circuit. We measured the operation bias margin of NDRO to be $\pm$15％. The circuit was measured at the liquid helium temperature.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2003년도 추계학술대회 논문집
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• pp.123-126
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• 2003

RSFQ (Rapid Single Flux Quantum) circuits are used in many practical applications. RSFQ DFFC (Delay Flip-Flop with complementary outputs) circuits can be used in a RAM, an ALU (Arithmetic Logic Unit), a microprocessor, and many communication devices. A DFFC circuit has one input, one switch input, and two outputs (output l and output 2). DFFC circuit functions in such way that output 1 follows the input and output 2 is the complement of the input when the switch input is "0." However, when there is a switch input "1."the opposite output signals are generated. In this work, we have designed an RSFQ DFFC circuit based on 1 ㎄/$\textrm{cm}^2$ niobium trilayer technology. As circuit design tools, we used Xic, WRspice, and Lmeter After circuit optimization, we could obtain the bias current margins of the DFFC circuit to be above 32％.