• Journal of Power Electronics
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• v.8 no.2
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• pp.171-180
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• 2008

One of the major problems in electric power quality is the harmonic contents. There are several methods of indicating the quantity of harmonic contents. The most widely used measure is the total harmonic distortion (THD). Various switching techniques have been used in static converters to reduce the output harmonic content. This paper presents and compares the two harmonic optimization techniques, known as optimal minimization of the total harmonic distortion (OMTHD) technique and optimized harmonic stepped-waveform (OHSW) technique used in multi-level inverters with unequal dc sources. Both techniques are very effective and efficient for improving the quality of the inverter output voltage. First, we describe briefly the cascaded H-bridge multi-level inverter structure. Then, we present the switching algorithm for the inverter based on OHSW and OMTHD techniques. Finally, the results obtained for the two techniques are analyzed and compared. The results verify the effectiveness of the both techniques in multi-level voltage-source inverter with non-equal dc sources, clarifying the advantages of each technique.

• Journal of Power Electronics
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• v.16 no.2
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• pp.512-521
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• 2016

Cascaded H-bridge multilevel (CHBML) inverters usually include a large number of isolated dc-voltage sources. Some faults in the dc-voltage sources result in unequal cell dc voltages. Unfortunately, the conventional phase-shifted carrier (PSC) PWM method that is widely used for CHBML inverters cannot eliminate low frequency sideband harmonics when the cell dc voltages are not equal. This paper analyzes the principle of sideband harmonic elimination, and proposes an improved PSCPWM that can eliminate low frequency sideband harmonics under the condition of unequal dc voltages. In order to calculate the carrier phases, it is necessary to solve transcendental equations for low frequency sideband harmonic elimination. Therefore, an approach based on the artificial bee colony (ABC) algorithm is presented in this paper. The proposed PSCPWM method enhances the reliability of CHBML inverters. The proposed PSCPWM is not limited to CHBML inverters. It can also be applied to other types of multilevel inverters. Simulation and experimental result obtained from a prototype CHBML inverter verify the theoretical analysis and the achievements made in this paper.

• Journal of Power Electronics
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• v.11 no.6
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• pp.811-818
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• 2011

Modulation strategies for multilevel inverters have typically focused on synthesizing a desired set of sinusoidal voltage waveforms using a fixed number of dc voltage sources. This makes the average power drawn from different dc voltage sources unequal and time varying. Therefore, the dc voltage sources are unregulated and require that corrective control action be incorporated. In this paper, first two new selections are proposed for determining the dc voltage sources values for asymmetric cascaded multilevel inverters. Then two modulation strategies are proposed for the dc power balancing of these types of multilevel inverters. Using the charge balance control methods, the power drawn from all of the dc sources are balanced except for the dc source used in the first H-bridge. The proposed control methods are validated by simulation and experimental results on a single-phase 21-level inverter.

• Journal of international Conference on Electrical Machines and Systems
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• v.1 no.1
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• pp.77-83
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• 2012

In this paper, an optimal solution to the harmonic reduction problem in a cascaded multilevel inverter with non-equal DC sources using a genetic algorithm (GA) is presented. Switching angles are generated for different values of modulation index by the proposed algorithm, considering minimum voltage total harmonic distortion (THD) whereas selected harmonics are controlled within the allowable limits at all desired modulation indices including the point of discontinuity. Results are stored as a look-up table to be used to control the inverter for a certain operating point. The computed angles are used in a simulated circuit in Matlab\Simulink to validate the results.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1610-1620
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• 2015

A major problem in conventional multilevel inverter is that an increase in power semiconductor switches causes an increase in cost and switching losses of the inverter. The multicarrier strategy adopted for the multilevel inverters has become more popular due to reduced cost, lower harmonic distortion, and higher voltage capability than the conventional switching strategy applied to inverters. Various topologies and modulation strategies have been reported for utility and drive applications. Level shifted based pulse width modulation techniques are proposed to investigate the performance of the multilevel inverter. The proposed work focuses on reducing the utilized switches so that the cost and the switching losses of the inverter do not go up and the consistent efficiency could be achieved. This paper presents the detailed analysis of these topologies. The analysis is based on the number of switches, DC sources, output level, maximum voltage, and the efficiency. As an illustration, single phase cascaded multilevel inverter topologies are simulated using MATLAB/SIMULINK and the experimental results demonstrate the viability of these inverters.

• Journal of Power Electronics
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• v.18 no.4
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• pp.1051-1066
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• 2018

This study presents a novel step-up switched capacitor multilevel inverter (SCMLI) structure. The proposed structure comprises 2 unequal DC voltage sources, 4 capacitors, and 14 unidirectional power switches. It can synthesize 21 output voltage levels. The important features of the proposed topology are its self-voltage boosting and inherent capacitor voltage balancing capabilities. Furthermore, a cascaded structure of the proposed SCMLI with an asymmetric DC voltage source configuration is presented. The proposed topology and its cascaded structure are compared with conventional and other recently developed topologies in terms of different aspects, such as the required components to produce a specific number of output voltage levels, the total standing voltage (TSV) and peak inverse voltage of the structure, and the maximum number of switches in the conducting path. Furthermore, a cost function is developed to verify the cost-effectiveness of the proposed topology with respect to other topologies. The TSV of the proposed topology is significantly lower than those of other topologies. Moreover, the developed topology is cost-effective compared with other topologies. A detailed operating principle, power loss analysis, and selection procedure for switched capacitors are presented for the proposed SCMLI structure. Extensive simulation and experimental studies of a 21-level inverter structure prove the effectiveness and merits of the proposed SCMLI.