• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 1998.03a
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• pp.84-87
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• 1998

• Proceedings of the SAREK Conference
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• 2007.06a
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• pp.185-185
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• 2007

• Journal of information and communication convergence engineering
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• v.2 no.2
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• pp.102-105
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• 2004

A Quadrature phase detector for high-speed delay-locked loop is introduced. The proposed Quadrature phase detector is composed of two nor gates and it determines if the phase difference of two input clocks is 90 degrees or not. The delay locked loop circuit including the Quadrature phase detector is fabricated in a 0.18 um Standard CMOS process and it operates at 5 GHz frequency. The phase error of the delay-locked loop is maximum 2 degrees and the circuits are robust with voltage, temperature variations.

• Proceedings of the KSR Conference
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• 2008.11b
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• pp.1084-1089
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• 2008

In this paper, a method for determining the boundary conditions which are derived from the random obstacles on the curves was presented. An algorism using this method is also developed. This determination method can be used for a good engineering tool in optimal curve design and an Radius-transition curve length(R-$L_t$) combination within the permissible zone can be improved without any increased costs.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.401-402
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• 2009

4-2 compressor는 곱셈기의 부분 곱 합 트리(partial product summation tree)의 기본적인 구성요소이다. 본 논문은 고속 연산이 가능한 4-2 compressor 구조를 제안한다. 제안한 회로는 최적화된 XORXNOR와 MUX로 구성하였다. 이 회로는 기존의 회로와 비교하였을 때 회로 구성에 필요한 트랜지스터수가 12개 감소하였으며, 지연시간이 32.2% 감소하였다. 제안한 회로는 Samsung 0.18um CMOS 공정을 이용하여 HSPICE로 시뮬레이션 하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.405-406
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• 2009

4-2 compressor는 곱셈기의 부분 곱 합 트리(partial product summation tree)의 기본적인 구성요소이다. 본 논문은 저 전력 특성을 갖는 4-2 compressor 구조를 제안한다. 제안한 회로는 한 개의 전가산기와 MUX로 구성하였다. 이 회로는 기존의 회로와 비교하였을 때 회로 구성에 필요한 트랜지스터수가 14개 감소하였으며, 6.3%의 전력소모가 감소하였다. 제안한 회로는 Samsung 0.18um CMOS 공정을 이용하여 HSPICE로 시뮬레이션 하였다.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.5
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• pp.587-592
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• 2015

According to increase in the use of the LED, the demand for low power consumption LED display design of the controller block has increased. In this paper, the low power LED controller block was designed through the power source supply that leads adiabatic operation from constant current source circuit operated by digital signal control. The proposed circuit was implemented using a 0.35um CMOS process. and it demonstrated linear operation of the circuit. From the simulation result, the proposed circuit was evaluated with about 82% power consumption reduction effect in comparison with conventional LED controller block. This research is expected to be helpful for the low power operation and the solution for heat problem of LED display.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.44-47
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• 2008

In this paper, a new circuit is proposed to minimize the charging and discharging current mismatch in charge pump for UWB PLL application. By adding a common-gate and a common-source amplifier and building the feedback voltage regulator, the high driving charge pump currents are accomplished. The proposed circuit has a wide operation voltage range, which ensures its good performance under the low power supply. The circuit has been implemented in an IBM 0.13um CMOS technology with 1.2V power supply. To evaluate the design effectiveness, some comparisons have been conducted against other circuits in the literature.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.185-193
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• 2014

In this paper, we developed a 4-channel particle counter for measuring particles, temperature, humidity in production facilities of clean-room environment, and the measured data can be transmitted via bluetooth. To measure the particle size ranging 0.3um~5um, we designed optical lens, particle detection chamber and multi-channel particle detection circuit. And we also developed a FMS program for real-time monitoring of measuring data, which resulted in the stable operation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.352-352
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• 2008

폐 자기회로 구조를 갖는 Meander 형태의 Inductor 설계를 위해 HFSS 프로그램을 이용하여 Meander Inductor를 시뮬레이션 하였다. Meander Inductor의 turn 수(N) 및 폭(W), 두께(T), 랩(G)의 변화에 따른 인덕턴스(L), S-parameter(S)와 Q-factor(Q)의 변화를 HFSS 를 통해 측정하였다. Al2O3 기판과 MgO의 두께는 각각 680um, 50um로 고정하였고, silver electrode를 이용하여 Meander 타입의 Inductor를 설계하였다. Meander Inductor의 turn수(6,7,8turn)의 변화를 측정한 결과, 8턴이었을 때 Q-factor가 19로서 가장 높은 결과를 얻었다. L의 결과 값은 공진 주파수와 의 관계에 의해 6turn일 때 L값은 17GHz에서 공진현상이 나타났다. 또한 W, G, T에 변화를 주어 설계한 뒤 시뮬레이션의 결과 값을 측정하였다. 그 값을 서로 비교한 결과, 변수들의 변화에 따라 L값과 Q-factor가 변화되었다. 이 논문에서는 각 변수에 따른 meander inductor의 특성을 HFSS 시뮬레이션을 통해 비교하고자 한다.