• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.1
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• pp.33-40
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• 1998

The composite SiO$_2$/Si$_3$N$_4$/SiO$_2$(ONO) film formed by oxidation on nitride film has been widely studied as DRAM stacked capacitor multi-dielectric films. Load lock(L/L) LPCVD system by HF cleaning is used to improve electrical capacitance and to scale down of effective thickness for memory device, but is brings a new problem. Nitride film deposited using HF cleaning shows selective deposition on poly silicon and oxide regions of capacitor. This problem is avoidable by carpeting chemical oxide using $H_2O$$_2$cleaning before nitride deposition. In this paper, we study the limit of nitride thickness for abnormal oxidation and the initial deposition time for nitride deposition dependent on underlayer materials. We proposed an advanced fabrication process for stacked capacitor in order to avoid selective deposition problem and show the usefulness of nitride deposition using L/L LPCVD system by $H_2O$$_2$cleaning. The natural oxide thickness on polysilicon monitor after HF and $H_2O$$_2$cleaning are measured 3~4$\AA$, respectively. Two substrate materials have the different initial nitride deposition times. The initial deposition time for polysilicon is nearly zero, but initial deposition time for oxide is about 60seconds. However the deposition rate is constant after initial deposition time. The limit of nitride thickness for abnormal oxidation under the HF and $H_2O$$_2$cleaning method are 60$\AA$, 48$\AA$, respectively. The results obtained in this study are useful for developing ultra thin nitride fabrication of ONO scaling and for avoiding abnormal oxidation in stacked capacitor application.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.326-329
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• 2002

In this paper, we investigated a feasibility of cerium oxide(CeO$_2$) films as a buffer layer of MFIS(metal ferroelectric insulator semiconductor) type capacitor. CeO$_2$ layer were Prepared by two step process of a low temperature film growth and subsequent RTA (rapid thermal annealing) treatment. By app1ying an ultra thin Ce metal seed layer and N$_2$ Plasma treatment, dielectric and interface properties were improved. It means that unwanted SiO$_2$ layer generation was successfully suppressed at the interface between He buffer layer and Si substrate. The lowest lattice mismatch of CeO$_2$ film was as low as 1.76% and average surface roughness was less than 0.7 m. The Al/CeO$_2$/Si structure shows breakdown electric field of 1.2 MV/cm, dielectric constant of more than 15.1 and interface state densities as low as 1.84${\times}$10$\^$11/ cm$\^$-1/eV$\^$-1/. After N$_2$ plasma treatment, the leakage current was reduced with about 2-order.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.7
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• pp.1229-1234
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• 2008

In this work, ultra high-voltage (17 - 50 kV AC), reliable 80 pF mica capacitors for partial discharge system application were investigated. Mica was used as the dielectric of the capacitors. Using the conservative design rule, over 3 individual $50\;{\mu}m$ thick mica sheets with a size of 30mm{\times}35mm were used with lead foils to form a parallel capacitor element and 20 mica sheets were interleaved with lead foils to form a series stack of parallel capacitor element to meet the requirements of the capacitors. The dimensions of the fabricated 80 pF capacitors for 17 kV AC and 50 kV AC were $90\;mm{\times}90\;mm$ and $95\;mm{\times}180\;mm$, respectively. The high-frequency characteristics of the capacitance (C) and dissipation factor (D) of the developed capacitors were measured using a capacitance meter. The developed capacitors exhibited C of 79.5 - 87.5 pF, had D of 0.001% over the frequency ranges of 150 kHz to 50 MHz, had a self-resonant frequency of 65 MHz, and showed results comparable to those measured for the capacitors prepared recently by $Adwel^{Tm}$. The developed capacitors also showed excellent characteristics for thermal shock test and temperature cycling test.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.202-207
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• 2015

A CMOS relaxation oscillator, with high robustness over process, voltage and temperature (PVT) variations, is designed in $0.18{\mu}m$ CMOS. The proposed oscillator, consisting of full-differential charge-discharge timing circuit and switched-capacitor based voltage-to-current conversion, could be expanded to a simple open-loop frequency synthesizer (FS) with output frequency digitally tuned. Experimental results show that the proposed oscillator conducts subcarrier generation for frequency-modulated ultra-wideband (FM-UWB) transmitters with triangular amplitude distortion less than 1%, and achieves frequency deviation less than 8% under PVT and phase noise of -112 dBc/Hz at 1 MHz offset frequency. Under oscillation frequency of 10.5 MHz, the presented design has the relative FS error less than 2% for subcarrier generation and the power dissipation of 0.6 mW from a 1.8 V supply.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.155-158
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• 1998

MLS capacitor with lipid ultra thin films were deposited by Langmuir-Blodgett (LB) method on the sillicon wafer. The current versus voltage and capacitance versus voltage relationships are depend on the applied voltage, electrode area and electrode materials. LB films deposited were made of L-$\alpha$-DLPC, the 1 layer's thickness of 35$\AA$ was measured by ellipsometer. And MLS capacitor with different electrode materials, the work function of these materials was investigated to increase the leakage current. The result indicated the lower leakage current and very high saturation value of capacitance was reached within 700-800 pF when the two electrode was Ag. And $\varepsilon$$_1$, $\varepsilon$$_2$ versus photon energy showed good film formation.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.717-720
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• 2007

We fabricated the 3.5 inch QCIF AMOLED panel with ultra low temperature polycrystalline silicon TFT on the plastic substrate. To reduce the leakage current, we used the triple layered gate metal structure. To reduce the stress from inorganic dielectric layer, we applied the organic interlayer dielectric and the photoactive insulating layer. By using the interlayer dielectric as a capacitor, the mask steps are reduced up to five.

• Electrical & Electronic Materials
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• v.4 no.1
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• pp.38-44
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• 1991

본 연구는 전기로에 의한 열 산화법에 의해 SiO$_{2}$(88[.angs.])와 ONO(89[.angs.])를 성장시켜 MIS capacitor를 제작한 후, 초 박막 유전체/실리콘 계면에서 전자파 간섭 효과를 실험적으로 비교 검토한 것이다. EWIE현상의 결과로서 첫째. 저 전계영역에 비해 고 전계영역에서 우세하며 둘째. SiO$_{2}$에 비해 ONO가 약하게 나타난다. 그러므로 ONO가 SiO$_{2}$보다 열 전송자 효과에 대한 저항성이 우수함을 알 수 있고 ULSI급의 게이트 절연막으로서의 실용가능성을 확인하였다.

• Journal of the Korean Ceramic Society
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• v.46 no.2
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• pp.146-154
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• 2009

It is necessary to minimize the thickness of Ni inner electrode layer and to improve the coverage of inner electrode, for the purpose of developing the ultra high-capacity multi layered ceramic capacitor (MLCC). Thus, low temperature sintering of dielectric $BaTiO_3$ ceramic should be precedently investigated. In this work, the relationship between dielectric properties of MLCC and batch condition such as mixing and milling methods was investigated in the $BaTiO_3$(BT)-Dy-Mg-Ba system with borosilicate glass as a sintering agent. In addition, several chip properties of MLCC manufactured by low temperature sintering were compared with conventionally manufactured MLCC. It was found that low temperature sintered MLCC showed better DC-bias property and lower aging rate. It was also confirmed that the thickness of Ni inner electrode layer became thinner and the coverage of inner electrode was improved through low temperature sintering.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.36-40
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• 2013

A novel design method of ultra wideband bandpass filter using CRLH transmission line with Dumbell type DGS is presented in this paper. Defected Ground Structure and microstrip interdigital capacitor are used to design the ultra wideband (UWB) filter. CRLH transmission line has composite characteristics of low pass and high pass filter. As control of cutoff frequency of low pass and high pass response on CRLH transmission line, we can get characteristic of UWB filter. We designed and simulated for CRLH transmission lines with one, two, four, and eight cells. A UWB filter using four cells CRLH is designed and fabricated to verify the results. The characteristics of designed filter have center frequency of 5GHz and relative bandwidth of 88%.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.208-211
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• 2005

This paper presents an ultra-low partial discharge(PD) measurement system that has been accepted as a non-destructive method to estimate electrical insulation of low-voltage electric devices. The PD measurement system is composed of a coupling network, a low noise amplifier, and associated electronics. A shielding box is used to make a better condition against electromagnetic interference. A low cut-off frequency of the coupling network was 1MHz(-3 dB). Calibration tests on laboratory set-up have shown that the PD measurement system has a stable sensitivity of 11.4mV/pC. In an application experiment on a low-voltage induction motor(5HP), we could detect 0.77pC level of partial discharge pulse at the applied voltage of AC 664 V$_{peak}$.