• 신재생에너지
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• 제20권1호
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• pp.116-125
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• 2024

Ultra-low-head is an unexplored classification among the sites in which hydroelectric power can be produced. This is typically owing to the low power output and the economic value of the turbines available in this segment. A turbine capable of operating in an ultra-low-head condition without the need of a dam to produce electricity is developed in this study. A gate structure installed at a shallow water channel acting as a weir generates artificial head for the turbine mounted on the gate to produce power. The turbine and generator are designed to be compact and submersible for an efficient and silent operation. The gate angle is adjustable to operate the turbine at varying flow rates. The turbine is designed and tested using computational fluid dynamics tools prior to manufacturing and experimental studies. A parametric study of the runner blade parameters is conducted to obtain the most efficient blade design with minimal hydraulic losses. These parameters include the runner stagger and runner leading edge flow angles. The selected runner design showed improved hydraulic characteristics of the turbine to operate in an ultra-low-head site with minimal losses.

• 사물인터넷융복합논문지
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• 제6권2호
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• pp.11-18
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• 2020

사물인터넷 (IoT, Internet of Things)의 최종단 장치들은 배터리로 운영되는 제품군이므로 초저전력(Ultra-low power: ULP)에 대한 세심한 고려가 필요하다. 마이크로 컨트롤러 (Micro Controller Unit: MCU) 업계는 에너지 절약을 위해 매우 효과 적인 기능을 개발해 왔으며, 제조사 별로 서로 다른 에너지 소비를 줄일 수 있는 여러 가지 동작 모드를 적용하고 있기 때문에, 개발자들은 MCU 선택에 어려움을 겪을 수 있다. 따라서, 본 논문에서는 다양한 벤더 및 기능 세트의 MCU를 비교할 수 있는 표준화 된 벤치마크 방법인 ULPMark 벤치마크에 대해서 소개하고, 이 평가에서 우수한 평가를 받은 2개의 플랫폼이 초저전력 동작을 위해 제공하고 있는 하드웨어 기능에 대해서 분석하였다. 또한, 드라이버 API와 세부 레지스터 제어를 통해 개발자들이 이 기능 들을 활용할 수 있는 방법에 대해 조사하고 분석 하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.159-165
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• 2016

Recently, active efforts are being made for future Si CMOS technology by various researches on emerging devices and materials. Capability of low power consumption becomes increasingly important criterion for advanced logic devices in extending the Si CMOS. In this work, a junctionless field-effect transistor (JLFET) with ultra-thin poly-Si (UTP) channel is designed aiming the sub-10-nm technology for low-power (LP) applications. A comparative study by device simulations has been performed for the devices with crystalline and polycrystalline Si channels, respectively, in order to demonstrate that the difference in their performances becomes smaller and eventually disappears as the 10-nm regime is reached. The UTP JLFET would be one of the strongest candidates for advanced logic technology, with various virtues of high-speed operation, low power consumption, and low-thermal-budget process integration.

• ETRI Journal
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• 제31권2호
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• pp.243-245
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• 2009

A novel ultra-low-power readout circuit for a pH-sensitive ion-sensitive field-effect transistor (ISFET) is proposed. It uses an ISFET/reference FET (REFET) differential pair operating in weak-inversion and a simple current-mode metal-oxide semiconductor FET (MOSFET) translinear circuit. Simulation results verify that the circuit operates with excellent common-mode rejection ability and good linearity for a single pH range from 4 to 10, while only 4 nA is drawn from a single 1 V supply voltage.

• 반도체공학회 논문지
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• 제2권1호
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• pp.9-16
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• 2024

본 논문에서는 무선 센서 네트워크를 위한 생체이식형 초저전력 MICS RF 트랜시버 설게에 대해 다룬다. 400 MHz MICS 표준은 WBAN 무선 센서 시스템 구현을 위해, 인체 내 전파적 특성 및 주변 네트워크와의 간접 최소화하며 고려되었다. 본 논문은 MICS 표준에 부합하는 시스템 및 송수신기 설계를 위한 link budget 및 다양한 송수신 아키텍쳐, 초저전력 송수신기 회로기법을 포함한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.625-626
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• 2006

An Ultra low power super-regenerative oscillator was implemented with on-chip inductor and quench signal generator. The super-regenerative oscillator detects the signal level as low as -70dBm while consuming only 0.48mA at 1.5V supply voltage. These results indicate that the super-regenerative oscillator can be outstanding candidate the simple, ultra low power receiver design.

• 한국초전도ㆍ저온공학회논문지
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• 제8권1호
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• pp.26-28
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• 2006

The development technique of digital logic using CMOS device is close reached several limitations These make technical needs that are ultra high speed superconductive systems based on CMOS silicon digital computing technique. Comparing digital logic based on silicon CMOS, the computing technique based on ultra high speed superconductive systems has many advantages which are ultra low power consumption, ultra high operation speed. etc. It is estimated that features like these increasingly improve the possibility of ultra low power and ultra superconductive systems. In this paper digital logics of current CMOS technique and RSFQ superconductive technique are compared with and analyzed.

• 전력전자학회논문지
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• 제26권3호
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• pp.199-204
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• 2021

Ultra-compact electric vehicles have narrow space for power conversion devices. This work presents schemes to achieve the high-power density of a low-voltage DC-DC converter (LDC): simplifying a converter structure by using sync-buck topology, applying a planar inductor using PCB winding, and applying a plate-type heat sink. The heat sink is placed between two PCBs, which increases the contact surface between the PCB and the heat-dissipating device. It enables the miniaturization of the converter to improve the conditions of heat radiation. The validity of the proposed scheme is verified through the experiment using a 500 W(12 V, 41.67 A) prototype with an input voltage range from 58 V to 84 V.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.210-216
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• 2004

In this paper, we propose a noncoherent On-Off Keying (OOK) Ultra Wide Band (UWB) system based on power detection with noise power calibration for low power applications. The proposed UWB system achieves good bit error rate performance which is favorably comparable to that of the system using the ideal adaptive threshold, while maintaining simple receiver structure, In addition, low power Analog Front-End (AFE) blocks for the proposed noncoherent UWB transceiver are proposed and verified using CMOS technology. Simulation results on the pulse generator, delay time generator and 1-bit Analog-to-Digital (AID) converter show feasibility of the proposed UWB AFE system.

• 전자통신동향분석
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• 제33권6호
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• pp.24-33
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• 2018

In the age of IoT, in which everything is connected to a network, there have been increases in the amount of data traffic, latency, and the risk of personal privacy breaches that conventional cloud computing technology cannot cope with. The idea of edge computing has emerged as a solution to these issues, and furthermore, the concept of ultra-low power edge intelligent semiconductors in which the IoT device itself performs intelligent decisions and processes data has been established. The key elements of this function are an intelligent semiconductor based on artificial intelligence, connectivity for the efficient connection of neurons and synapses, and a large-scale spiking neural network simulation framework for the performance prediction of a neural network. This paper covers the current trends in ultra-low power edge intelligent semiconductors including issues regarding their technology and application.