• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.1
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• pp.414-435
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• 2017

As network adaptive streaming technology becomes increasingly common, transport protocol also becomes important in guaranteeing the quality of multimedia streaming. At the same time, because of the appearance of high-quality video such as Ultra High Definition (UHD), preventing buffering as well as preserving high quality while deploying a streaming service becomes important. The Internet Engineering Task Force recently published Multipath TCP (MPTCP). MPTCP improves the maximum transmission rate by simultaneously transmitting data over different paths with multiple TCP subflows. However, MPTCP cannot preserve high quality, because the MPTCP subflows slowly increase the transmission rate, and upon detecting a packet loss, drastically halve the transmission rate. In this paper, we propose a new multipath congestion control scheme for high-quality multimedia streaming. The proposed scheme preserves high quality of video by adaptively adjusting the increasing parameter of subflows according to the network status. The proposed scheme also increases network efficiency by providing load balancing and stability, and by supporting fairness with single-flow congestion control schemes.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2013.06a
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• pp.113-116
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• 2013

최근 방송, 의료, 우주산업, 게임, UCC, 핸드폰 등 여러 사업 분야에 걸쳐 실제에 근접한 영상을 요구하고 있고 이것은 3D와 Ultra High Definition (UHD) 영상의 출현으로 현실화 되고 있다. UHD 급에 걸맞는 압축률을 위해 Joint Collaborative Team on Video Coding (JCT-VC) 에서는 MPEG-4 Part 10 AVC/H.264를 뒤이을 차세대 코덱으로 High Efficiency Video Coding (HEVC) 를 개발을 시작했다. HEVC는 기존 MPEG-4 Part 10 AVC/H.264코덱과 비교해 40%이상의 압축률을 나타내지만 복잡도 역시 상승했다. 특히 복호화기에서 복잡도는 중요한 요소이며, 역 코사인변환 (Inverse Discrete Cosine Transform, IDCT) 은 전체 복호화시간의 8% ~ 16%를 차지하는 알고리즘이다. 본 논문에서는 IDCT 의 수행시간을 줄이기 위해 병렬프로그래밍 중의 하나인 SIMD명령어를 사용하여 효율적으로 병렬화 프로그래밍을 하는 기법들을 제안한다. 본 제안 기법은 IDCT 수행시간을 평균 59% 단축하는 결과를 보였다.

• Journal of Broadcast Engineering
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• v.23 no.5
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• pp.606-613
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• 2018

This study is concerned with implementing an external memory expansion device for large-scale image processing. It consists of an external memory adapter card with a PCI(Peripheral Component Interconnect) Express Gen3 x8 interface mounted on a graphics workstation for image processing and an external memory board with external DDR(Dual Data Rate) memory. The connection between the memory adapter card and the external memory board is made through the optical interface. In order to access the external memory, both Programmable I/O and DMA(Direct Memory Access) methods can be used to efficiently transmit and receive image data. We implemented the result of this study using the boards equipped with Altera Stratix V FPGA(Field Programmable Gate Array) and 40G optical transceiver and the test result shows 1.6GB/s bandwidth performance.. It can handle one channel of 4K UHD(Ultra High Density) image. We will continue our study in the future for showing bandwidth of 3GB/s or more.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.10
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• pp.2479-2496
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• 2013

Increasing demand for Full High-Definition (FHD) video and Ultra High-Definition (UHD) video services has led to active research on high speed video processing. Widespread deployment of multi-core systems has accelerated studies on high resolution video processing based on parallelization of multimedia software. Even if parallelization of a specific decoding step may improve decoding performance partially, such partial parallelization may not result in sufficient performance improvement. Particularly, entropy decoding has often been considered separately from other decoding steps since the entropy decoding step could not be parallelized easily. In this paper, we propose a parallelization technique called Integrated Multi-Threaded Parallelization (IMTP) which takes parallelization of the entropy decoding step, with other decoding steps, into consideration in an integrated fashion. We used the Simultaneous Multi-Threading (SMT) technique with appropriate thread scheduling techniques to achieve the best performance for the entire decoding step. The speedup of the proposed IMTP method is up to 3.35 times faster with respect to the entire decoding time over a conventional decoding technique for H.264/AVC videos.

• Electronics and Telecommunications Trends
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• v.31 no.3
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• pp.70-80
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• 2016

고품질 영상 서비스에 대한 사람들의 관심이 커짐에 따라 몇 해 전부터 Ultra High Definition(UHD)와 같은 초고해상도 기술을 이용한 영상 서비스가 화두가 되고 있으며 이를 위한 다양한 연구들이 진행되고 있다. 이런 변화와 더불어 최근 카메라에서 촬영된 원본과 같은 사실감을 느낄 수 있도록 고명암비(High Dynamic Range: HDR)와 광색역(Wide Color Gamut: WCG)을 지원하는 기술에 대한 관심이 높아지고 있으며 관련 연구와 표준화가 활발히 진행되고 있다. 본고에서는 이러한 기술적 흐름에 발맞추어 HDR/WCG의 기본 개념과 각 요소 기술들에 대해 살펴보고 더불어 HDR/WCG 영상 서비스를 위한 다양한 표준단체들의 표준화 활동에 대해서도 한번 살펴보고자 한다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2013.06a
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• pp.180-181
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• 2013

High efficiency video coding (HEVC) appears due to the demand on high compression video coding beyond H.264/AVC in ultra-high definition (UHD) videos. As for intra prediction, HEVC has 35 prediction modes while H.264/AVC has 9 intra modes. To exploit the spatial correlation, we adopt an edge detection method, establish the edge map, and adaptively select the candidate modes using the acquired edge information in a block. The number of the candidate modes is determined through trade-off between computational complexity and coding efficiency. Besides, the range of coding unit sizes is determined using the uniqueness of the edge directions for the given image block. As a result, we reduced the encoding time by 56.8% at the cost of 2.5% BD-BR increase on average compared to Full modes at the HEVC reference software (HM 6.0 [1]).

• Journal of Broadcast Engineering
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• v.19 no.6
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• pp.767-788
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• 2014

The worldwide transition from analog to digital broadcasting has now been completed and the need to study next generation standards for Ultra High Definition TV (UHDTV) broadcasting, and broadcasting & communication convergence systems is rapidly growing. In particular, high resolution mobile broadcasting services are needed to satisfy recent consumers. Therefore, the development of highly efficient convergence broadcasting systems that provide fixed/mobile broadcasting through a single channel is needed. In this paper, a service scenario and requirements for providing 4K UHD & HD convergence broadcasting services through a terrestrial single channel are analyzed by employing the latest transmission and A/V codec technologies. Optimized transmission parameters for 6 MHz & 8 MHz terrestrial bandwidths are drawn, and receiving performances are measured under Additive White Gaussian Noise (AWGN) and time-varying multipath channels. From the results, in a 6 MHz bandwidth, the reliable receiving of HD layer data can be achieved when the receiver velocity is maximum 140 Km/h and is not achieved when the velocity is over 140 Km/h due to the limit of bandwidth. When the bandwidth is extended to 8 MHz, the reliable receiving of both 4K UHD and HD layer data is achieved under a very fast fading multipath channel.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.169-177
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• 2015

This paper proposes a hardware architecture for an efficient SAO(Sample Adaptive Offset) with low area for HEVC(High Efficiency Video Coding) encoder. SAO is a newly adopted technique in HEVC as part of the in-loop filter. SAO reduces mean sample distortion by adding offsets to reconstructed samples. The existing SAO requires a great deal of computational and processing time for UHD(Ultra High Definition) video due to sample by sample processing. To reduce SAO processing time, the proposed SAO hardware architecture processes four samples simultaneously, and is implemented with a 2-step pipelined architecture. In addition, to reduce hardware area, it has a single architecture for both luma and chroma components and also uses optimized and common operators. The proposed SAO hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 190k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 200MHz, it can support 4K UHD video encoding at 60fps in real time, but operates at a maximum of 250MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.11
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• pp.1364-1373
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• 2016

Ultra High Definition Television (UHDTV) has attracted much attention as one of next generation broadcasting services. For the commercialization of UHD broadcasting service, standardization groups including the DVB (Digital Video Broadcasting) and the ATSC (Advanced Television Systems Committee) have decided to adopt the Orthogonal Frequency Division Multiplexing (OFDM) for signal transmission. However, when the carrier frequency is not properly synchronized at the receiver, inter-symbol interference (ISI) and inter-carrier interference (ICI) may occur. In order to avoid performance degradation resulting from ISI or ICI, receivers should synchronize the carrier frequency by using preambles and pilot symbols. However, there only few published literature dealing with the frequency offset estimation methods regarding the next generation terrestrial broadcasting. In this respect, this paper proposes a method to estimate timing and fractional frequency offset for the ATSC 3.0 system by using a preamble bootstrap symbol. The proposed detector can detect the fractional frequency offset by adding a complex conjugate product on the conventional estimator where only timing offset can be estimated.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.112-120
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• 2013

In this paper, we propose high-performance H.264/AVC CAVLC encoder for UD video real time processing. Statistical values are obtained in one cycle through the parallel arithmetic and logical operations, using non-zero bit stream which represents zero coefficient or non-zero coefficient. To encode codeword per one cycle, we remove recursive operation in level encoding through parallel comparison for coefficient and escape value. In oder to implement high-speed circuit, proposed CAVLC encoder is designed in two-stage {statical scan, codeword encoding} pipeline. Reducing the encoding table, the arithmetic unit is used to encode non-coefficient and to calculate the codeword. The proposed architecture was simulated in 0.13um standard cell library. The gate count is 33.4Kgates. The architecture can support Ultra Definition Video ($3840{\times}2160$) at 100 frames per second by running at 100MHz.