• Journal of the Semiconductor & Display Technology
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• v.20 no.4
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• pp.108-113
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• 2021

In this paper, a totem pole PFC was structured in two methods with FET and diode for low-speed switch while GaN FET was used for high-speed switch. Internal power loss, power conversion efficiency and steady-state characteristics of the two methods were compared in the totem pole bridgeless PFC circuit which is widely applied in large-capacity and high-efficiency switching rectifier of 500W or more. In order to compare and confirm the steady-state characteristics under equal conditions, a 2kW class totem pole bridgeless PFC was constructed and the experimental results were analyzed. From the experimental results, it was confirmed that the low-speed switch operation has a large difference in efficiency due to the internal conduction loss of the low-speed switch at a low input voltage. Especially, input power factor and load characteristic showed no difference regardless of the low-speed switch operation.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.357-360
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• 2003

In this paper, we investigated the characteristics of 4${\times}$4 thermo-optic switch using two mode interference(TMI) coupler. We designed this matrix switch by using a configuration which combines a double Mach- Zehnder interferometer(MZI) switching unit. The average extinction ratio and average excess loss of the 4${\times}$4 thermo-optic switch was 33.7dB, 0.29dB, respectively.

• Journal of Power Electronics
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• v.18 no.4
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• pp.1007-1014
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• 2018

A novel dual DC-DC flyback converter with leakage-energy recycling is presented in this paper. Only an active switch is used for this converter. A pulse-width-modulation strategy is adopeted to control this switch. Two transformers are employed for the proposed converter. During the switch ON-period, the primary windings of the two transformers store energies. At the switch OFF-period, the energies stored in the primary windings of the two transformers are released to the output via the secondary windings of the two transformers. Meanwhile, the leakage energies of the two transformers can be recycled. The operating principles and steady-state analyses of the proposed converter are described in detail. A prototype circuit of the proposed converter is implemented for verifying the performances.

• Progress in Superconductivity
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• v.7 no.1
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• pp.36-40
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• 2005

The problem of fluctuation-induced digital errors in a rapid single flux quantum (RSFQ) circuit has been a very important issue. In this work, we calculated the bit error rate of an RSFQ switch used in superconductive arithmetic logic unit (ALU). RSFQ switch should have a very low error rate in the optimal bias. Theoretical estimates of the RSFQ error rate are on the order of $10^{-50}$ per bit operation. In this experiment, we prepared two identical circuits placed in parallel. Each circuit was composed of 10 Josephson transmission lines (JTLs) connected in series with an RSFQ switch placed in the middle of the 10 JTLs. We used a splitter to feed the same input signal to both circuits. The outputs of the two circuits were compared with an RSFQ exclusive OR (XOR) to measure the bit error rate of the RSFQ switch. By using a computerized bit-error-rate test setup, we measured the bit error rate of $2.18{\times}10^{-12}$ when the bias to the RSFQ switch was 0.398 mA that was quite off from the optimum bias of 0.6 mA.

• Proceedings of the KIEE Conference
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• 2006.04b
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• pp.247-250
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• 2006

This paper presents the single-stage High Power Factor TSFC(Two-Switch Forward Converter). Recently, due to growing concern about the harmonic pollution of power distribution systems and the adoption of standards such as ICE 61000-3-2 and IEEE 519, There is a need to reduce the harmonic contents of AC line currents of power supplies. This research proposed the single-stage two switch forward circuit for low voltage and high current output. The principle of operation, feature and design considerations are illustrated and verified through the experiment with a 200W(5V, 40A) 200kHz MOSFET based experimental circuit.

• Proceedings of the KIEE Conference
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• 2006.10d
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• pp.169-172
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• 2006

This paper presents the single-stage High Power Factor AC/DC Two-Switch Forward Converter (TSFC). Recently, due to growing concern about the harmonic pollution of power distribution systems and the adoption of standards such as ICE 61000-3-2 and IEEE 519, There is a need to reduce the harmonic contents of AC line currents of power supplies. This research proposed the single-stage two switch forward circuit for low voltage and high current output. The principle of operation, feature and design considerations are illustrated and verified through the simulation with a 200W(5V, 40A) 200kHz MOSFET based experimental circuit.

• Journal of Electrical Engineering and Technology
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• v.8 no.5
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• pp.1107-1115
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• 2013

A new PWM technique for a two-phase BLDC motor fed by a two-phase eight-switch inverter is proposed in this paper. It is well known that a two-phase eight-switch inverter can significantly improve power output compared with a two-phase six-switch inverter in a two-phase motor drive. To drive the two-phase BLDC motor simply and effectively, two normal PWM strategies are investigated to manage speed regulation. However, under the conditions of low speed and light load, especially during the braking process, the current in a short time of one period is near zero, which is a discontinuous waveform every half period. To solve it, a novel PWM technique is investigated to improve the operational performance of normal technique. Using the new PWM scheme, the current continues every half period and the braking performance is improved. The effectiveness of the proposed PWM method is verified through the experiments.

• Progress in Superconductivity and Cryogenics
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• v.7 no.1
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• pp.21-24
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• 2005

The problem of fluctuation-induced digital errors in a rapid single flux quantum (RSFQ) circuit has been very important issue. So in this experiment, we calculated error rate of RSFQ switch in superconductiyity ALU, The RSFQ switch should have a very low error rate in the optimal bias. We prepared two circuits Placed in parallel. One was a 10 Josephson transmission lines (JTLs) connected in series, and the other was the same circuit but with an RSFQ switch placed in the middle of the 10 JTLs. We used a splitter to feed the same input signal to the both circuits. The outputs of the two circuits were compared with an RSFQ XOR to measure the error rate of the RSFQ switch. By using a computerized bit error rate test setup, we measured the bit error rate of 2.18$\times$$10^{12}$ when the bias to the RSFQ switch was 0.398mh that was quite off from the optimum bias of 0.6mA.

• Journal of Power Electronics
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• v.16 no.2
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• pp.786-797
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• 2016

This paper describes the design and development of a novel semiconductor-based solid-state switch for damped oscillating voltage test system. The proposed switch is configured as two identical series-connected switch stacks, each of which comprising 10 series-connected IGBT function units. Each unit consists of one IGBT, a gate driver, and an auxiliary voltage sharing circuit. A single switch stack can block 20 kV-rated high voltage, and two stacks in series are proven applicable to 30 kV-rated high voltage. The turn-on speed of the switch is approximately 250 ns. A flyback topology-based power supply system with a front-end power factor correction is built for the drive circuit by loosely inductively coupling each unit with a ferrite core to the primary side of a power generator to obtain the advantages of galvanic isolation and compact size. After the simulation, measurement, and estimation of the parasitic effect on the gate driver, a prototype is assembled and tested under different operating regimes. Experimental results are presented to demonstrate the performance of the developed prototype.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.119-130
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• 1996

This paper is the part I of the full study about improved structure of fully interconnected ATM switch to develop the small sized switch element and practical implemention of switch network. This part I paper describes about proposed switch structure, performance evaluations and some of considerations to practical implementation. The proposed structure is constructed of two step buffering scheme in a filtered multiplexer. First step buffering is carried out by small sized dedicated buffers located at each input port. And second step buffering is provided by a large sized common buffer at the output port. To control bursty traffic, we use speed up factor in multiplexing and priority polling according to the levels of buffer occupancy. Proposed structure was evaluated by computer simulation with two evaluation points. One is comparision of multiplexing discipline between hub polling and priority polling. The ogher is overall which should be considered to improve the practical implementation.