• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.272-281
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• 2013

This paper presents low power frequency shift keying (FSK) transmitter using all digital PLL (ADPLL) for smart utility network (SUN). In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The FSK transmitter is implemented in $0.18{\mu}m$ 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is $3.5mm^2$. The power consumption of the ADPLL is 12.43 mW. And, the power consumptions of the transmitter are 35.36 mW and 65.57 mW when the output power levels are -1.6 dBm and +12 dBm, respectively. Both of them are supplied by 1.8 V voltage source. The frequency resolution of the TDC is 2.7 ps. The effective DCO frequency resolution with the differential MOS varactor and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.8 GHz is -121.17 dBc/Hz with a 1 MHz offset.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2007.05a
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• pp.417-420
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• 2007

Micro parts are usually used of producing by micro-electro-mechanical systems(MEMS). In this paper, we present some fundamental results concerning on the MEMS, extrusion condition on the micro forming characteristics and new micro forward extrusion machine has been developed. In the first step, we manufactured micro dies in two kinds of sections. One is a circle section, another is a cross section. The process for fabricating micro dies combines a deep UV-lithography, anisotropic etching techniques and metal electroplating with bulk silicon based on Ni with a thickness of $50{\mu}m$. The outer diameter of Ni-micro dies is 3mm and the diameter of extrusion section is $270{\mu}m$ for a cross section, $500{\mu}m$ for a circle section. The low linear density polyethylene(LLEPD) in the shape of a pellet has been used of micro extrusion. The billet was placed in a container manufactured by electric discharge machining and extruded through the micro die by a piezoelectric actuator. The micro extrusion has succeeded in a forming such micro parts as micro bars, micro cross shafts.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.28 no.1
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• pp.125-132
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• 2010

With recent advancement of remote sensing technology, a variety of data acquisition over the same area is achievable. An automated co-registration of heterogeneous airborne images is a critical step for change detection. This paper describes an automatic method for co-registration between digital image and existing building model. Optimal building models for co-registration purpose are extracted as primitives from existing building model database. A set of homologous features between straight lines extracted from aerial digital image and model primitive are computed based on geometric similarity function. With obtained homologous features, EO parameter is recomputed using least square method. The result shows that die suggested method automatically co-register two data set in a reliable manner.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• Korean Journal of Head & Neck Oncology
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• v.33 no.2
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• pp.1-8
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• 2017

Cancer is the disease of aging and Korea is one of the fastest aging country in the world. Older patients have decreased organ function and stress tolerance, therefore are at high risk of functional decline and developing complication from cancer and cancer treatment. Before beginning cancer treatment, it is important to assess patients' life expectancy, whether the patient is likely to die of cancer or of other comorbidity, and also the risks with cancer treatment. In order to estimate patient's physiologic age, it is recommended to perform geriatric assessment and implement appropriate geriatric intervention together with meticulous supportive care, when planning cancer treatment for older patients. In a resource limited country such as Korea, two step approach of applying screening tool followed by geriatric assessment can be more efficient. Geriatric assessment is used to predict toxicity from cancer treatment such as surgery, radiotherapy, and chemotherapy, predict survival, and also to aid treatment decision. Number of randomized trials are ongoing to compare usual care versus oncogeriatric care, and with these results we expect to improve outcome of older patients with cancer.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.04a
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• pp.819-823
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• 1996

In the large steel ingosts, void defects exhibiting microvoid shapes are inevitably formed in the V-segregation zone of the ingots during solidification. In the hot open-die forging process, material properties are improved by eliminating internal porosity. The void size is practically very small as compared with the huge large ingot. Thus, for deformation analysis of a large ingot, a massive number of elements are needed in order to describe a void surface and to uniform mesh sturcture. In the present work the Global/Local scheme has been introduced in order to reduce the computational time and to easily generate the mesh system as a void module of local mesh for obtaining the accurate solution around a void. The procedure of the global- local method consists of two steps. In the first step global analysis is carried out which seeks a reasonably good solution with a cpurse mesh system without describing a void. Then, a local analysis is performed locally with a fine mesh system under the size-criterion of a local region. The computational time has been greatly reduced. Though the work it has been shown that large ingot forging incorporation small voids can be effectively analyzed by using the proposed Global/Local scheme.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2002.05a
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• pp.29-32
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• 2002

The mechanical joining process of a sheet metal pair has been developed in order to replace the resistance spot welding process in case that joining of mechanically unweldable materials and coated sheet metals with different thickness are needed. Form-joining or clinching, a kind of mechanical joining process, is defined as joining process of a sheet metal pair by geometric constraint imposed by plastic deformation of workpieces without any additive part. It has been reported that the joining strength by commercial form-joining apparatus is 50∼70 percent of that by resistance spot welding. Therefore, a two-step form-joining process with a secondary punch is proposed. The device is designed to improve the joining strength by increasing the geometric constraint of the deformed shape by combining a primary punch, a secondary punch and a female die. In order to verify the improved joining strength by the designed process, the tensile-shear strength, the peel-tension strength and the asymmetric peel-tension strength are compared with those by the TOX process and resistance spot welding.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.29-33
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• 2012

The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.

• Advanced Composite Materials
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• v.17 no.1
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• pp.1-23
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• 2008

Robotized filament winding technology involves a robot that winds a roving impregnated by resin on a die along the directions of stresses to which the work-piece is submitted in applications. The robot moves a deposition head along a winding trajectory in order to deposit roving. The trajectory planning is a very critical aspect of robotized filament winding technology, since it is responsible for both the tension constancy and the winding time. The present work shows two original rules to plan the winding trajectory of structural parts, whose shape is obtained by sweeping a full section around a 3D curve that must be closed and not crossing in order to assure a continuous winding. The first rule plans the winding trajectory by approximating the part 3D shape with straight lines; it is called the discretized rule. The second rule defines the winding trajectory simply by offsetting a 3D curve that reproduces the part 3D shape, of a defined distance; it is called the offset rule. The two rules have been compared in terms of roving tension and winding time. The present work shows how the offset rule enables achievement of both the required aims: to manufacture parts of high structural performances by keeping the tension on the roving near to the nominal value and to markedly decrease the winding time. This is the first step towards the optimization of the robotized filament winding technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.87-93
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• 2010

This paper presents a high resolution, wide input range 2-step time-to-digital converter used in digital PLL. TDC is used to compare the DPLL output frequency with reference frequency and should be implemented with high resolution to improve the phase noise of DPLL. The conventional TDC consists of delay line realized inverters, whose resolution is determined by delay time of inverter and transistor size, resulting in limited resolution. In this paper, 2-step TDC with phase-interpolation and Time Amplifier is proposed to meet the high resolution and wide input range by implement the delay time less than an inverter delay. The gain of Time Amplifier is improved by using the delay time difference between two inverters. It is implemented in $0.13{\mu}m$ CMOS process and the die area is $800{\mu}m{\times}850{\mu}m$ Current consumption is 12 mA at the supply voltage of 1.2 V. The resolution and input range of the proposed TDC are 0.357 ps and 200 ps, respectively.