• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.9
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• pp.18-26
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• 1993

This paper presents a multiplier free technique for the complex DFT by rotations and additions based on the complex approximation of the ring of algebraic integers. Speeding-up the computation time and reducing the dynamic range growth has been achieved by the elimination of multiplication. Moreover the DFT of no twiddle factor quantization errors is possible. Numerical examples are given to prove the algorithm and the applicable size of the DFT is 16 has been concluded.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.107-110
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• 2001

In this paper, we propose a multiplication-free DFT kernel computation technique, whose input sequences are approximated into a ring of Algebraic Integers. This paper also gives computational examples for DFT and IDFT. And we proposes an architecture of the DFT using barrel shifts and adds. When the radix is greater than 4, the proposed method has a high Precision property without scaling errors due to twiddle factor multiplication. A possibility of higher radix system assumes that higher performance can be achievable for reducing the DFT stages in FFT.

• Korean Journal of Mathematics
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• v.19 no.3
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• pp.243-253
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• 2011

We would like to propose a Cooley-Tukey modied algorithm in fast Fourier transform(FFT). Of course, this is a kind of Cooley-Tukey twiddle factor algorithm and we focused on the choice of integers. The proposed algorithm is better than existing ones in speeding up the calculation of the FFT.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.5-8
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• 2002

In this paper, we are designed and verified a FFT/IFFT processor that is possible from the wireless LAN environment which is adopted international standard of the IEEE802.11a. The proposed architecture of the FFT/IFFT has Radix-2 64point SDF(single-path delay feedback) Pipeline technique and DIF(Decimation in Frequenct) structure. The FFT/IFFT processor has each 8 bit complex input-output and 6 bit Twiddle factor. we used Max-PlusII for simulation and can see that processor is properly operated

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.1 s.307
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• pp.101-108
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• 2006

In this paper, an efficient butterfly structure for Radix-4 FFT algorithm using DA(Distributed Arithmetic) is proposed. It is shown that DA can be efficiently used in twiddle factor calculation of the Radix-4 FFT algorithm. The Verilog-HDL coding results for the proposed DA butterfly structure show $61.02\%$ cell area reduction comparison with those of the conventional multiplier butterfly structure. furthermore, the 64-point Radix-4 pipeline structure using the proposed butterfly and delay commutators is compared with other conventional structures. Implementation coding results show $46.1\%$ cell area reduction. Due to its efficient processing scheme, the proposed FFT structure can be widely used in large size of FFT like OFDM Modem.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.3
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• pp.103-110
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• 2008

In this paper, an efficient butterfly structure for 8K/2K-Point Radix-4 FFT algorithm using CORDIC(coordinate rotation digital computer) is proposed. It is shown that CORDIC can be efficiently used in twiddle factor calculation of the Radix-4 FFT algorithm. The Verilog-HDL coding results for the proposed CORDIC butterfly structure show 36.9% cell area reduction comparison with those of the conventional multiplier butterfly structure. Furthermore, the 8K/2K-point Radix-4 pipeline structure using the proposed butterfly and delay commutators is compared with other conventional structures. Implementation coding results show 11.6% cell area reduction. Due to its efficient processing scheme, the proposed FFT structure can be widely used in large size of FFT like OFDM Modem.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.8
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• pp.116-121
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• 2005

To realize the tap coefficient of a finite impulse response(FIR) filter or the twiddle factor of a fast Fourier transform(FFT) using a current-mode analog circuit, a high accurate current-attenuator circuit is needed This paper introduces an accuracy enhancement technique in the current-mode signal processing. First of all, the DC of set-current error in a conventional current-attenuator using a gate-ratioed orient mirror circuit is analyzed and then, the current-attenuator circuit with a negligibly small DC offset-current error is introduced. The circuit consists of N-output current mirrors connected in parallel with me another. The output current of the circuit is attenuated to 1/N of the input current. On the basis of the Kirchhoff current law, the current scale ratio is determined simply by the number of the current mirrors in the N-current mirrors connected in parallel. In the proposed current-attenuator circuit the scale accuracy is limited by the ac gain error of the current mirror. Considering that a current mirror has a negligibly small ac gain error, the attainable maximum scale accuracy is theoretically -80[dB] to the input current.

• ETRI Journal
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• v.44 no.3
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• pp.379-388
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• 2022

This study proposes a novel low-complexity algorithm for computing inverse fast Fourier transform (IFFT)/fast Fourier transform (FFT) operations in binary phase shift keying-modulated orthogonal frequency division multiplexing (OFDM) communication systems without requiring any twiddle factor multiplications. The peak-to-average power ratio (PAPR) reduction capacity of an efficient PAPR reduction technique, that is, H-SLM method, is evaluated using the proposed IFFT algorithm without any complex multiplications, and the impact of oversampling factor for the accurate calculation of PAPR is analyzed. The power spectral density of an OFDM signal generated using the proposed multiplierless IFFT algorithm is also examined. Moreover, the bit-error-rate performance of the H-SLM technique with the proposed IFFT/FFT algorithm is compared with the classical methods. Simulation results show that the proposed IFFT/FFT algorithm used in the H-SLM method requires no complex multiplications, thereby minimizing power consumption as well as the area of IFFT/FFT processors used in OFDM communication systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.963-972
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• 2002

An 8192-point pipelined FFT/IFFT processor core is designed, which can be used in multi-carrier modulation systems such as DUf-based VDSL modem and OFDM-based DVB system. In order to improve the signal-to-quantization-noise ratio (SQNR) of FFT/IFFT results, two-step convergent block floating-point (TS_CBFP) scaling is employed. Since the proposed TS_CBFP scaling does not require additional buffer memory, it reduces memory as much as about 80% when compared with conventional CBFP methods, resulting in area-and power-efficient implementation. The SQNR of about 60-㏈ is achieved with 10-bit input, 14-bit internal data and twiddle factors, and 16-bit output. The core synthesized using 0.25-$\mu\textrm{m}$ CMOS library has about 76,300 gates, 390K bits RAM, and twiddle factor ROM of 39K bits. Simulation results show that it can safely operate up to 50-㎒ clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. It was verified by Xilinx FPGA implementation.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.1071-1074
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• 2002

In this paper, power quality analysis system is proposed where voltage or current waveforms are nonsinusoidal. The proposed system relies on the FFT algorithm to compute real and reactive power. The advantage of system is that harmonic analysis is carried out on a period of the input signal. The proposed system is based on FFT processor which is designed using VHDL(Very high-speed integrated circuit Hardware Description Language). In the design of FFT processor, radix- $2^2$ is adopted to reduce several complex multipliers for twiddle factor. Complex multiplier is implemented as only shifters and adders. Therefore, the system is able to have both high hardware efficiency and high performance.