• 제목/요약/키워드: Tunnel field-effect transistor

검색결과 33건 처리시간 0.017초

Hf0.5Zr0.5O2 강유전체 박막의 다양한 분극 스위칭 모델에 의한 동역학 분석 (Switching Dynamics Analysis by Various Models of Hf0.5Zr0.5O2 Ferroelectric Thin Films)

  • 안승언
    • 한국재료학회지
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    • 제30권2호
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    • pp.99-104
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    • 2020
  • Recent discoveries of ferroelectric properties in ultrathin doped hafnium oxide (HfO2) have led to the expectation that HfO2 could overcome the shortcomings of perovskite materials and be applied to electron devices such as Fe-Random access memory (RAM), ferroelectric tunnel junction (FTJ) and negative capacitance field effect transistor (NC-FET) device. As research on hafnium oxide ferroelectrics accelerates, several models to analyze the polarization switching characteristics of hafnium oxide ferroelectrics have been proposed from the domain or energy point of view. However, there is still a lack of in-depth consideration of models that can fully express the polarization switching properties of ferroelectrics. In this paper, a Zr-doped HfO2 thin film based metal-ferroelectric-metal (MFM) capacitor was implemented and the polarization switching dynamics, along with the ferroelectric characteristics, of the device were analyzed. In addition, a study was conducted to propose an applicable model of HfO2-based MFM capacitors by applying various ferroelectric switching characteristics models.

Schottky 장벽 접합을 이용한 MOS형 소자의 소오스/드레인 구조의 특성 (The characteristics of source/drain structure for MOS typed device using Schottky barrier junction)

  • 유장열
    • 전자공학회논문지T
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    • 제35T권1호
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    • pp.7-13
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    • 1998
  • Submicron급의 고집적 소자에서는 종래의 긴 채널 소자에서 생기지 않던 짧은 채널효과에 기인하는 2차원적인 영향으로 고온전자(hot carrier) 등이 발생하여 소자의 신뢰성을 저하시키는 요인이 되고 있어 이들의 발생을 최소화할 수 있는 다양한 형상의 소오스/드레인 구조가 연구되고 있다. 본 논문에서는 제작공정의 간략화, 소자규모의 미세화, 응답속도의 고속화에 적합한 소오스/드레인에 Schottky장벽 접합을 채택한 MOS형 트랜지스터를 제안하고, p형 실리콘을 이용한 소자의 제작을 통하여 동작특성을 조사하였다. 이 소자의 출력특성은 포화특성이 나타나지 않는 트랜지스터의 작용이 나타났으며, 전계효과 방식의 동작에 비하여 높은 상호콘덕턴스를 갖고 있는 것으로 나타났다. 여기서 고농도의 채널층을 형성하여 구동 전압을 낮게하고 높은 저항의 기판을 사용하므로서 드레인과 기판사이의 누설전류를 감소시키는 등의 개선점이 있어야 할 것으로 나타났다.

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Single Junction Charge Pumping 방법을 이용한 전하 트랩형 SONOSFET NVSM 셀의 기억 트랩분포 결정 (Determination of Memory Trap Distribution in Charge Trap Type SONOSFET NVSM Cells Using Single Junction Charge Pumping Method)

  • 양전우;홍순혁;서광열
    • 한국전기전자재료학회논문지
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    • 제13권10호
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    • pp.822-827
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    • 2000
  • The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor field effect transistor) NVSM (nonvolatile semiconductor memory) cell is investigated by single junction charge pumping method. The device was fabricated by 0.35㎛ standard logic fabrication process including the ONO stack dielectrics. The thickness of ONO dielectricis are 24$\AA$ for tunnel oxide, 74 $\AA$ for nitride and 25 $\AA$ for blocking oxide, respectively. By the use of single junction charge pumping method, the lateral profiles of both interface and memory traps can be calculated directly from experimental charge pumping results without complex numerical simulation. The interface traps were almost uniformly distributed over the whole channel region and its maximum value was 7.97$\times$10$\^$10/㎠. The memory traps were uniformly distributed in the nitride layer and its maximum value was 1.04$\times$10$\^$19/㎤. The degradation characteristics of SONOSFET with write/erase cycling also were investigated.

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