• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.2
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• pp.91-100
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• 2011

The Triple Data Encryption Algorithm (Triple DES) is an international standard of block cipher, which composed of two encryption processes and one decryption process of DES to increase security level. In this paper, we proposed a Differential Fault Analysis (DFA) attack to retrieve secret keys using reduction of last round execution for each DES process in the Triple DES by fault injections. From the simulation result for the proposed attack method, we could extract three 56-bit secret keys using exhaustive search attack for $2^{24}$ candidate keys which are refined from about 9 faulty-correct cipher text pairs. Using laser fault injection experiment, we also verified that the proposed DFA attack could be applied to a pure microprocessor ATmega 128 chip in which the Triple DES algorithm was implemented.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.4
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• pp.709-717
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• 2012

The round reduction on block cipher is a fault injection attack in which an attacker inserts temporary errors in cryptographic devices and extracts a secret key by reducing the number of operational round. In this paper, we proposed an improved round reduction method to retrieve master keys by injecting a fault during operation of loop statement in the Triple DES. Using laser fault injection experiment, we also verified that the proposed attack could be applied to a pure microprocessor ATmega 128 chip in which the Triple DES algorithm was implemented. Compared with previous attack method which is required 9 faulty-correct cipher text pairs and some exhaustive searches, the proposed one could extract three 56-bit secret keys with just 5 faulty cipher texts.

• Proceedings of the Korea Multimedia Society Conference
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• 2000.04a
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• pp.117-120
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• 2000

This paper describe VLSL design of crytographic processor which can execute triple DES and DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has 1 unrolled loop structure without pipeline and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation , the key precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O techniques is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is implemented using Altera EPF10K40RC208-4 devices and has peak performance of about 75 Mbps under 20 Mhz ECB DES mode and 25 Mbps uder 20 Mhz triple DES mode.

• Korean Journal of Clinical Pharmacy
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• v.22 no.2
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• pp.113-122
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• 2012

ACC/AHA/SCAI Guideline recommends for administration dual antiplatelet therapy after drug-eluting stent (DES) to prevent restenosis and stent thrombosis in patients with percutaneous coronary intervention (PCI). Recently triple antiplatelet therapy including cilostazol is known to reduce restenosis and stent thrombosis significantly after DES implantation. However, there is lack of data providing the efficacy of triple antiplatelet therapy. The purpose of this study is to evaluate the clinical effects of the triple therapy after DES implantation compared with the dual therapy. This retrospective study collected data from medical charts of 251 patients who received DES implantation between Jul 2006 and Jun 2008. They received either dual antiplatelet therapy (N = 154 clopidogrel and aspirin; Dual group) or triple antiplatelet therapy (N = 97 cliostazol, clopidogrel and aspirin; Triple group). Major adverse cardiac event rates (MACE, included total death, myocardial infarction, target lesion revascularization) at 12 months, 24 months, stent thrombosis, rates of bleeding complications and adverse drug reactions were compared between these two groups. Compared with the dual group, the triple group had a similar incidence of the MACE rates at 24months (12.3% vs. 12.4%, p = 0.99). There is no difference in overall stent thrombosis between two groups (Dual group 2.6% vs. Triple group 4.1%, p = 0.5). Subgroup analysis showed that diabetic patients got more benefit in reducing MACE rates but, there is no statistical difference. Bleeding complications and adverse drug effects were not different significantly. As compared with dual antiplatelet therapy, triple antiplatelet therapy did not reduce the 12-months, 24-months MACE rates and stent thrombosis. Bleeding complications and adverse drug effects were not different.

• Proceedings of the Korea Information Assurance Society Conference
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• 2004.05a
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• pp.59-64
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• 2004

In this paper a design and an implementation of a crypto chip which implements SEED and Triple-DES algorithms are described. We designed it by VHDL(VHSIC Hardware Description Language) which is a designed system-description language. To apply the chip to various application, four operating Modes such as ECB, CBC, CFB, and CFB are supported. The chip was designed by the Virtex-E XCV2000E BG560 of Xilinx and we confirmed result of it at the FPGA implementation by functional and timing simulation using the Xilinx Foundation Series 3.li.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.41-48
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• 2013

An efficient encryption algorithm based on the Data Encryption Standard (DES) for personal cloud computing environments is presented. The proposed algorithm improves data privacy, security and also encryption speed, compared with the triple DES. The improvement of the proposed algorithm stems from enhanced privacy inherent from the use of spread random interleaver in the place of the known substitution table for initial and final permutations in the DES algorithm. The simulation results demonstrate that the interleaver based DES (I-DES) is found to run faster than the triple DES algorithm and also offer improved security. The proposed algorithm also offers encryption for variable-length data using the Cipher Block Chaining (CBC).

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.169-172
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• 2000

This paper describes design of cryptographic processor which can execute SEED, DES, and triple DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has I unrolled loop structure with hardware sharing and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation, the precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O technique is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is designed using 2.5V 0.25 $\mu\textrm{m}$ CMOS technology and consists of about 34.8K gates. Its peak performances is about 250 Mbps under 100 Mhz ECB SEED mode and 125 Mbps under 100 Mhz triple DES mode.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.4
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• pp.298-302
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• 2011

In this paper, we propose an efficient encryption algorithm for ensuring data privacy and security for cloud computing in mobile environments. As part of the evaluation of the proposed algorithm, we have implemented the algorithm in a PC environment and compared with the well-known encryption algorithm of the Data Encryption Standard (DES). The conventional DES algorithm is hard to maintain privacy, due to the fact that its initial and final permutation are known to the network To prevent this critical weakness, a triple DES algorithm has been reported, but it has a disadvantage of long encryption time. In this study, we propose random interleaving algorithm that uses the permutation table for improving privacy further. The proposed algorithm is found to run faster than the triple DES algorithm and also offers improved security in a wireless communication system.

• Journal of KIISE:Information Networking
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• v.29 no.6
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• pp.625-634
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• 2002

Cryptography is the methods of making and using secret writing that is necessary to keep messages private between two parties. Cryptography is compute-intensive algorithm and needs cpu resource excessively. To solve these problems, there exists hardware approach that implements cryptographic algorithm with hardware chip. In this paper, we presents the design and implementation of cryptographic hardware and compares its performance with software cryptographic algorithms. The experimental result shows that the hardware approach causes high I/O overheads when it transmits data between cryptographic board and host cpu. Hence, low complexity cryptographic algorithms such as DES does not improve the performance. But high complexity cryptographic algorithms such as Triple DES improve the performance with a high rate, roughly from two times to Sour times.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.940-943
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• 2002

This paper presents hardware implementations of the two representative cryptographic algorithms, Advanced Encryption Standard (Rijndael), and the present American federal standard (Triple DES) using a PCI- based FPGA board named "EBSW-1" This board bases on a FPGA chip (Xilinx Virtex300 XCV300PQ240-4). The implementation results of these two algorithms were tested successfully. AES circuit could proceed an encryption as well as a decryption two times faster than the Triple-DES circuit, while the former circuit used higher rates of CLBs. Besides, if these architectures use pipeline-registers, the processing speed will be increased about 1.5 times than the presented circuits.