• Title/Summary/Keyword: Triggered based Memory

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Telemetry Performance Enhancement Based on Spectral Efficient Retransmission (주파수 효율적 재전송 기반 원격측정 성능 향상)

  • Park, Chung-woon;Park, Hyo Sub
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.45 no.5
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    • pp.429-436
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    • 2017
  • Since the telemetry performance using the time-delayed data dissipates the wireless channel resources, we propose the spectral efficient retransmission scheme in this paper. In the proposed scheme, the telemetry data is retransmitted based on triggered memory to improve the spectral efficiency. The proposed scheme minimizes the error caused by multipath fading, antenna pattern as well as the error caused by the flight events. In the flight simulation data, we show the proposed scheme improves the telemetry performance based on spectral efficient retransmission.

Design & Implementation of the RMMC and Global Time based on the RT-eCos 3.0 (RT-eCos 3.0 기반의 RMMC 및 글로벌 타임 설계 및 구현)

  • Han, Seoung-Yeon;Kim, Jung-Guk
    • Journal of KIISE:Computing Practices and Letters
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    • v.16 no.7
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    • pp.759-767
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    • 2010
  • RT-eCos 3.0 is a micro-sized embedded real-time kernel that has been developed based on the open source eCos 3.0 to support the basic task model of the well-known distributed real-time object model, TMO(Time-Triggered Message-triggered Object). In this paper, the design and implementation techniques of the RMMC(Real-time Multicast & Memory replication Channel) that is a standard distributed IPC model of the TMO is described based on the RT-eCos 3.0. And the support technique of the global time for using the same time in a distributed environment using the RMMC is also described. The developed global time based RMMC supports highly abstracted distributed IPC environment in a wide area distributed computing environment with the RT-eCos 3.0.

I/O Translation Layer Technology for High-performance and Compatibility Using New Memory (뉴메모리를 이용한 고성능 및 호환성을 위한 I/O 변환 계층 기술)

  • Song, Hyunsub;Moon, Young Je;Noh, Sam H.
    • Journal of KIISE
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    • v.42 no.4
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    • pp.427-433
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    • 2015
  • The rapid advancement of computing technology has triggered the need for fast data I/O processing and high-performance storage technology. Next generation memory technology, which we refer to as new memory, is anticipated to be used for high-performance storage as they have excellent characteristics as a storage device with non-volatility and latency close to DRAM. This research proposes NTL (New memory Translation layer) as a technology to make use of new memory as storage. With the addition of NTL, conventional I/O is served with existing mature disk-based file systems providing compatibility, while new memory I/O is serviced through the NTL to take advantage of the byte-addressability feature of new memory. In this paper, we describe the design of NTL and provide experiment measurement results that show that our design will bring performance benefits.

Design and Implementation of the Extended SLDS for Real-time Location Based Services (실시간 위치 기반 서비스를 위한 확장 SLDS 설계 및 구현)

  • Lee, Seung-Won;Kang, Hong-Koo;Hong, Dong-Suk;Han, Ki-Joon
    • Journal of Korea Spatial Information System Society
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    • v.7 no.2 s.14
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    • pp.47-56
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    • 2005
  • Recently, with the rapid development of mobile computing, wireless positioning technologies, and the generalization of wireless internet, LBS (Location Based Service) which utilizes location information of moving objects is serving in many fields. In order to serve LBS efficiently, the location data server that periodically stores location data of moving objects is required. Formerly, GIS servers have been used to store location data of moving objects. However, GIS servers are not suitable to store location data of moving objects because it was designed to store static data. Therefore, in this paper, we designed and implemented an extended SLDS(Short-term Location Data Subsystem) for real-time Location Based Services. The extended SLDS is extended from the SLDS which is a subsystem of the GALIS(Gracefully Aging Location Information System) architecture that was proposed as a cluster-based distributed computing system architecture for managing location data of moving objects. The extended SLDS guarantees real-time service capabilities using the TMO(Time-triggered Message-triggered Object) programming scheme and efficiently manages large volume of location data through distributing moving object data over multiple nodes. The extended SLDS also has a little search and update overhead because of managing location data in main memory. In addition, we proved that the extended SLDS stores location data and performs load distribution more efficiently than the original SLDS through the performance evaluation.

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Design of a Pipeline Processor for the Automated ECG Diagnosis in Real Time (실시간 심전도 자동진단을 위한 파이프라인 프로세서의 설계)

  • 이경중;윤형로;이명호
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.8
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    • pp.1217-1226
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    • 1989
  • This paper describes a design of hardware system for real time automatic diagnosis of ECG arrhythmia based on pipeline processor consisting of three microcomputer. ECG data is acquisited by 12 bit A/D converter with hardware QRS triggered detector. Four diagnostic parameters-heart rate, morpholigy, axis, and ST segment-are used for the classification and the diagnosis of arrhythmia. The functions of the main CPU were distributed and processed with three microcomputers. Therefore the effective data process and the real time process using microcomputer can be obtained. The interconnection structure consisting of two common memory unit is designed to decrease the delay time caused by data transfer between processors and be which the delay time can be taken 1% of one clock period.

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Design of Pipeline Processor for ECG Feature Extraction (ECG 특징추출을 위한 파이프라인 프로세서의 설계)

  • 이경중;윤형로
    • Journal of Biomedical Engineering Research
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    • v.9 no.1
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    • pp.79-86
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    • 1988
  • This paper describes the design of a hardware systenl for ECG feature extraction based on pipeline processor consistinsf of three microcomputers. ECG data is acquisited by 12 bit A/D converter with hardware QRS triggered detector. Four diagnostic parameters parameters-heart rate, morPhology, axis, and 57 segment-are used for the classification and the diagnosis of arrhythmia. The functions of the main CPU were distributed and processed with three microcomputers. Therefore the effective data process and the real time process using microcomputer can be obtained. The interconnection structure consisting of two common memory units is designed to decrease the delay time caused by data transfer between processors and designed by which the delay time can be taken Loye of one clock period.

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EETCA: Energy Efficient Trustworthy Clustering Algorithm for WSN

  • Senthil, T.;Kannapiran, Dr.B.
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.10 no.11
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    • pp.5437-5454
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    • 2016
  • A Wireless Sensor Network (WSN) is composed of several sensor nodes which are severely restricted to energy and memory. Energy is the lifeblood of sensors and thus energy conservation is a critical necessity of WSN. This paper proposes a clustering algorithm namely Energy Efficient Trustworthy Clustering algorithm (EETCA), which focuses on three phases such as chief node election, chief node recycling process and bi-level trust computation. The chief node election is achieved by Dempster-Shafer theory based on trust. In the second phase, the selected chief node is recycled with respect to the current available energy. The final phase is concerned with the computation of bi-level trust, which is triggered for every time interval. This is to check the trustworthiness of the participating nodes. The nodes below the fixed trust threshold are blocked, so as to ensure trustworthiness. The system consumes lesser energy, as all the nodes behave normally and unwanted energy consumption is completely weeded out. The experimental results of EETCA are satisfactory in terms of reduced energy consumption and prolonged lifetime of the network.

A design of pipeline processor for real time ECG process (실시간 심전도 처리를 위한 파이프라인 프로세서의 설계)

  • Lee, Kyoung-Joong;Lee, Yoon-Sun;Yoon, Hyoung-Ro;Lee, Myoung-Ho
    • Proceedings of the KIEE Conference
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    • 1988.07a
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    • pp.731-733
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    • 1988
  • This paper describes a design of hardware system for real time automatic diagnosis of ECG arrhythmia based on pipeline processor consisting of the three microcomputer. ECG data is acquisited by 12 bit A/D converter with hardware QRS triggered detector. Four diagnostic parameters - heart rate, morphology, axis, and ST segment - are used for the classification and the diagnosis of arrhythmia. The functions of the main CPU were distributed and processed with three microcomputers. There-fore the effective data process and the real time process using microcomputer can be obtained. The interconnection structure consisting of two common memory units is designed to decrease the delay time caused by data transfer between processors and by which the delay time can be taken 1 % of one clock period.

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Compiler triggered C level error check (컴파일러에 의한 C레벨 에러 체크)

  • Zheng, Zhiwen;Youn, Jong-Hee M.;Lee, Jong-Won;Paek, Yun-Heung
    • The KIPS Transactions:PartA
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    • v.18A no.3
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    • pp.109-114
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    • 2011
  • We describe a technique for automatically proving compiler optimizations sound, meaning that their transformations are always semantics-preserving. As is well known, IR (Intermediate Representation) optimization is an important step in a compiler backend. But unfortunately, it is difficult to detect and debug the IR optimization errors for compiler developers. So, we introduce a C level error check system for detecting the correctness of these IR transformation techniques. In our system, we first create an IR-to-C converter to translate IR to C code before and after each compiler optimization phase, respectively, since our technique is based on the Memory Comparison-based Clone(MeCC) detector which is a tool of detecting semantic equivalency in C level. MeCC accepts only C codes as its input and it uses a path-sensitive semantic-based static analyzer to estimate the memory states at exit point of each procedure, and compares memory states to determine whether the procedures are equal or not. But MeCC cannot guarantee two semantic-equivalency codes always have 100% similarity or two codes with different semantics does not get the result of 100% similarity. To increase the reliability of the results, we describe a technique which comprises how to generate C codes in IR-to-C transformation phase and how to send the optimization information to MeCC to avoid the occurrence of these unexpected problems. Our methodology is illustrated by three familiar optimizations, dead code elimination, instruction scheduling and common sub-expression elimination and our experimental results show that the C level error check system is highly reliable.

Metal-Insulator Transition of Vanadium Dioxide Based Sensors (바나듐 산화물의 금속-절연체 전이현상 기반 센서 연구)

  • Baik, Jeong Min
    • Journal of Sensor Science and Technology
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    • v.23 no.5
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    • pp.314-319
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    • 2014
  • Here, we review the various methods for the preparation of vanadium dioxide ($VO_2$) films and nanowires, and their potential applications to the sensors such as gas sensor, strain sensor, and temperature sensor. $VO_2$ is an interesting material on account of its easily accessible and sharp Mott metal-insulator transition (MIT) at ${\sim}68^{\circ}C$ in the bulk. The MIT is also triggered by the electric field, stress, magnetic field etc. This paper involves exceptionally sensitive hydrogen sensors based on the catalytic process between hydrogen molecules and Pd nanoparticles on the $VO_2$ surface, and fast responsive sensors based on the self-heating effects which leads to the phase changes of the $VO_2$. These features will be seen in this paper and can enable strategies for the integration of a $VO_2$ material in advanced and complex functional units such as logic gates, memory, FETs for micro/nano-systems as well as the sensors.