• Current Optics and Photonics
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• v.7 no.5
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• pp.574-581
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• 2023

A scheme is proposed to generate triangular waveforms with alterable symmetry. The key component is a cascaded single-drive Mach-Zehnder modulator (SD-MZM) and optical polarization beam splitter-combiner architecture. In this triangular waveform generator, the bias-induced phase shift, modulation index and controllable delay difference are changeable. To generate triangular waveform signals with different symmetry indexes, different combinations of these variables are selected. Compared with the previous schemes, this generator just contains one SD-MZM and the balanced photodetector (BPD) is not needed, which means the costs and energy consumption are significantly reduced. The operation principle of this triangular waveform generator has been theoretically analyzed, and the corresponding simulation is conducted. Based on the theoretical and simulated results, some experiments are demonstrated to prove the validity of the scheme. The triangular waveform signals with a symmetry factor range of 20-80% are generated. Both experiment and theory prove the feasibility of this method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.8
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• pp.1552-1557
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• 2007

In this work, temperature stable pulse width modulation controller using bandgap reference voltage is proposed. Two bandgap reference voltages are designed by using BiCMOS technology which are temperature dependent and independent voltage references. PWM controller is designed by using 3.3 volt supply voltage and the output frequency is 1MHz. From simulation results, the variation of output pulse width is less than form +0.86% to -0.38% in the temperature range $0^{\circ}C\;to\;70^{\circ}C$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.68-73
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• 2009

This paper describes design and implementation of a spread spectrum clock generator (SSCG) for the DisplayPort. The proposed architecture generates the spread spectrum clock using a sigma-delta fractional-N PLL. The SSCG uses a digital End order MASH 1-1 sigma-delta modulator and a 9bit Up/Dn counter. By using MASH 1-1 sigma-delta modulator, complexity of circuit and chip area can be reduced. The advantage of sigma-delta modulator is the better control over modulation frequency and spread ratio. The SSCG generates dual clock rates which are 270MHz and 162MHz with 0.25% down-spreading and triangular waveform frequency modulation of 33kHz. The peak power reduction is 11.1dBm at 270MHz. The circuit has been designed and fabricated using in 0.18$\mu$m CMOS technology. The chip occupies 0.620mm$\times$0.780mm. The measurement results show that the fabricated chip satisfies the DispalyPort standard.