• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.1
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• pp.13-18
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• 1999

The trap density by the stress bias in silicon oxides with different thicknesses has been investigated. The trap density by stress bias was shown to be composed of on time current and off time current. The on time trap density was composed of dc current. The off time trap density was caused by the tunneling charging and discharging of the trap in the interfaces. The on time trap density was used to estimate to the limitations on oxide thicknesses. The off time trap density was used to estimate the data retention in nonvolatile memory devices.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.645-647
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• 2008

In this paper, we analyzed interface trap density between pentacene and PVP and SiO2 gate dielectric by using high-low C-V characteristics. The interface trap density was $10^{13}\;cm^{-2}eV^{-1}$.

• 전기의세계
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• v.29 no.8
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• pp.511-518
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• 1980

The thermostimulated discharge currents of low-density polyethylene electrets were measured versus the principal experimental variables. Several electrode types were used for the charging and discharging procedures. The results led to know the experimental conditions for the heterocharge and homocharge accumulating and decreasing. The electronic structure parameters of polyethylene such as trap level, density of traps, hopping length, mobility, trap time constants were deduced. A method for evaluating the local electric field inside the electret is proposed.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.2
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• pp.17-24
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• 2000

In this paper, the stress and transient currents associated with the on and off time of applied voltage were used to measure the density and distribution of high voltage stress induced traps in thin silicon oxide films. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform new both cathode and anode interface. The trap densities were dependent on the stress polarity. The stress generated trap distributions were relatively uniform the order of 1011~1021[states/eV/cm2] after a stress voltage. It appear that the stress and transient current that flowed when the stress voltage were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.216.2-216.2
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• 2015

본 연구에서는 charge pumping method에서 사용되는 변수들의 변화를 이용하여 hot carrier stress가 MOSFET소자의 oxide내에서의 trap 분포에 어떤 영향을 미치는지에 대해서 연구하였다. trap 분포를 확인하기 위해 스트레스 전 후에 reverse bias와 주파수에 따른 trap의 양을 측정 하였다. 스트레스 전과 후에 reverse bias와 주파수가 감소할수록 trap이 증가하는 모습이 나타났고, 스트레스 후에는 전과 비교하여 전반적으로 trap의 양이 증가하였다. 또한, 스트레스 전과 후에 MOSFET소자의 trap density는 center region에서 $2.89{\times}$10^10에서 $1.64{\times}$10^10으로 감소하였고, drain region에서 $2.83{\times}$10^10에서 $5.26{\times}$10^10으로 증가한 것을 확인하였다. 이는 reverse bias와 주파수의 가변에 따라서 trap의 공간적 분포를 측정할 수 있다는 것을 의미한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.4
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• pp.56-61
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• 2015

Ideal and stretch-out C-V curve were shown at high frequency using SiGe p-FinFET simulation. Average interface trap density can be extracted by the difference of voltage axis on ideal and stretch-out C-V curve. Also, interface trap density(Dit) was extracted by Terman's method that uses the same stretch-out of C-V curve with interface trap characteristic, and average interface trap density was calculated at same energy level. Comparing the average interface trap density, which was found by method using difference of voltage, with Terman's method, it was verified that the two methods almost had the same average interface trap density.

• Journal of Sensor Science and Technology
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• v.31 no.4
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• pp.271-277
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• 2022

We analyzed the effects of the interface trap on the output characteristics of an inversion mode n-channel GaN Schottky barrier (SB)-MOSFET based on the N_it distribution using TCAD simulation. As interface trap number density (N_it) increased, the threshold voltage increased while the drain current density decreased. Under N_it=5.0×10¹⁰ cm^-2 condition, the threshold voltage was 3.2 V for V_DS=1 V, and the drain current density reduced to 2.4 mA/mm relative to the non-trap condition. Regardless of the N_it distribution type, there was an increase in the subthreshold swing (SS) following an increase in N_it. Under U-shaped N_it distribution, it was confirmed that the SS varied depending on the gate voltage. The interface fixed charge (Q_f) caused an shift in the threshold voltage and increased the off-state current collectively with the surface trap. In summary, GaN SB-MOSFET can be a building block for high power UV optoelectronic circuit provided the surface state is significantly reduced.

• Journal of the Korean Graphic Arts Communication Society
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• v.14 no.2
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• pp.21-36
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• 1996

With increased use of halftone dot overprints for offset color printing, it is important to study the density and ink trap of the overprints. In this research the equation to predict the density and the method to evaluate ideally the fractional ink trap are preposed. And also the halftone dot overprinting experiments of Magenta over Cyan or Cyan over Magenta under wet-on-wet or wet-on-dry overprinting using 2-color offset press show the above proposals are reasonable, and show the effect of overprinting sequence on the density and ink trap.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.43-46
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• 2000

In this paper, the stress and transient currents associated with the on and off time of applied voltage were used to measure the density and distribution of high voltage stress induced traps in thin silicon oxide films. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform near both cathode and anode interface. The trap densities were dependent on the stress polarity. The stress generated trap distributions were relatively uniform the order of $10^{11}\sim10^{21}$[states/eV/$cm^2$] after a stress. The trap densities at the oxide silicon interface after high stress voltages were in the $10^{10}\sim10^{13}$[states/eV/$cm^2$]. It appear that the stress and transient current that flowed when the stress voltage were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• Korean Journal of Organic Agriculture
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• v.19 no.spc
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• pp.214-217
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• 2011

When paprika is cultivated during summer season, thrips starts to occur in the early growing season and reaches its peak in late June. In the treatment using Orius laevigatus and Neoseiulus cucumeris, natural enemies to thrips, thrips density was 87.6/trap and 51.3/trap on June 23. After Orius laevigatus and Neoseiulus cucumeris were treated twice on June 24 and July 23, the number decreased considerably. On August 23, it was 36.9/trap and 40.3/trap and from the mid August to early September thrips density remained low. Effect of Orius laevigatus and Neoseiulus cucumeris on suppression of thrips density was 35.7% and 44.6% on July 22, however, the number went up to 88.8% and 80.5% on September 3.