• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.218-221
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• 2008

Bottom-gate microcrystalline silicon thin film transistors (${\mu}c$-Si:H TFTs) were fabricated on glass and transparent polyimide substrates by conventional 13.56 MHz RF plasma enhanced chemical vapor deposition at $200^{\circ}C$. The deposition rate of the ${\mu}c$-Si:H film is 24 nm/min and the amorphous incubation layer near the ${\mu}c$-Si:H/silicon nitride interface is unobvious. The threshold voltage of ${\mu}c$-Si:H TFTs can be improved by $H_2$ or $NH_3$ plasma pretreatment silicon nitride film.

• Journal of the Semiconductor & Display Technology
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• v.16 no.3
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• pp.59-64
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• 2017

As the demand on displays increases, new thin-film transistors such as metal oxide transistor are continuously being invented. When designing a circuit consisting of such new transistors, a new transistor model based on proper charge transport mechanisms is needed for each of them. In this paper, a modeling framework which enables to choose charge transport mechanisms that are limited to certain operation regions and assemble them into a transistor model instead of making an integrated transistor model dedicated to each transistor. The framework consists of a graphic user interface to choose charge transport models and a current calculation part, which is also implemented in AIM-SPICE for circuit simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.302-317
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• 2017

This paper proposes a new full adder design based on pass-transistor logic that offers ultra-low power dissipation and superior variability together with low transistor count. The pass-transistor logic allows device count reduction through direct logic realization, and thus leads to reduction in the node capacitances as well as short-circuit currents due to the absence of supply rails. Optimum transistor sizing alleviates the adverse effects of process variations on performance metrics. The design is subjected to a comparative analysis against existing designs based on Monte Carlo simulations in a SPICE environment, using the 22-nm CMOS Predictive Technology Model (PTM). The proposed ULP adder offers 38% improvement in power in comparison to the best performing conventional designs. The trade-off in delay to achieve this power saving is estimated through the power-delay product (PDP), which is found to be competitive to conventional values. It also offers upto 79% improvement in variability in comparison to conventional designs, and provides suitable scalability in supply voltage to meet future demands of energy-efficiency in portable applications.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.403-405
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• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1Tr FeFET) memory cell scheme, which select one unit memory cell and program/read it. The well voltage can be controlled by isolating the common row well lines. Through applying bias voltage to Gate and Well, respectively, we implement If FeFET memory cell scheme in which interference problem is not generated and the selection of each memory cell is possible. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.205-210
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• 2003

A 3-Transistor cell CMOS OTP ROM array using standard CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option as a high density OTP ROM array for modern digital as well as analog circuits.

• Journal of the Semiconductor & Display Technology
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• v.5 no.1 s.14
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• pp.17-20
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• 2006

This paper presents of a new type of memory cell that could potentially replace both DRAM and flash memory. The proposed device cell operates by sensing the state of about 1,000 electrons trapped between unique insulating barriers in the channel region of the upper transistor. These electrons are controlled by a side gate on the transistor, and their state in turn controls the gate of the larger transistor, providing signal gain within the memory cell. It becomes faster and more reliable memory with lower operation voltage. Moreover, the use of a multiple tunnel junction (MTJ) fur the vertical transistor can significantly improve the data retention and operation speed.

• Journal of IKEEE
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• v.17 no.4
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• pp.531-536
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• 2013

The impact of UV irradiation process on the AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistor was investigated. Due to the high intensity UV irradiation before the gate dielectric deposition, the conductivity of AlGaN/GaN structure and the drain saturation current of the transistor increased by about 10 %. However, the pinch off characteristics of transistor was severely deformed by the process. By comparing the electrical characteristics of the transistors, it was proposed that the high intensity UV irradiation formed a sub-channel under the two dimensional electron gas of AlGaN/GaN structure even without additional impurity injection.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.504-505
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• 2005

In this report, we demonstrate a high performance polymer thin-film transistor fabricated on a paper substrate. As a water barrier layer, parylene was coated on the paper substrate by using vacuum deposition process. Using poly (3-hexylthiophene) as an active layer, a polymer thin-film transistor with field-effect of up to 0.086 $cm^2/V{\cdot}s$ and on/off ratio of $10^4$ was achieved. The fabrication of polymer thin-film transistor built on a cheap paper substrate is expected to open a channel for future applications in flexible and disposable electronics with extremely low-cost.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1771-1773
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• 2007

Surface modification of the gate dielectric has a strong influence on the performance of printed transistors. The surface modification occurs between the gate dielectric and semiconductor. The printed transistor with evaporated vanadium pentoxide ($V_2O_5$) modification exhibits a mobility of $0.2cm^2\;V^{-1}\;s{-1}$ and a subthreshold slope of 1.47 V/decade.

• Journal of Sensor Science and Technology
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• v.32 no.6
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• pp.386-390
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• 2023

Stiffness-engineered stretchable substrate technology has been widely used to produce stretchable displays, transistors, and integrated circuits because it is compatible with various flexible electronics technologies. However, the stiffness-engineering technology has never been applied to transistor-based stretchable strain sensors. In this study, we developed thin-film transistor-based strain sensors on stiffness-engineered stretchable substrates. We designed and fabricated strain-sensitive stretchable resistors capable of inducing changes in drain currents of transistors when subjected to stretching forces. The resistors and source electrodes of the transistors were connected in series to integrate the developed stretchable resistors with thin-film transistors on stretchable substrates by printing the resistors after fabricating transistors. The thin-film transistor-based stretchable strain sensors demonstrate feasibility as strain sensors operating under strains of 0%-5%. This strain range can be extended with further investigations. The proposed stiffness-engineering approach will expand the potential for the advancement and manufacturing of innovative stretchable strain sensors.