• 제목/요약/키워드: Transfer switch

검색결과 204건 처리시간 0.024초

Technique of Coronary Transfer for TGA with Single Coronary Artery

  • Kim, Tae Ho;Jung, Jae Jun;Kim, Yong Han;Yang, Ji-Hyuk;Jun, Tae-Gook
    • Journal of Chest Surgery
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    • 제47권6호
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    • pp.529-532
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    • 2014
  • An eight-day-old neonate was diagnosed with dextro-transposition of the great arteries, atrial septal defect, patent ductus arteriosus, and a single sinus origin of the coronary arteries. The single coronary artery originated from the left sinus (sinus 2), had a proximal left circumflex arterial branch, and passed anteriorly to the right side of the aorta, further branching into the right coronary and left anterior descending arteries. We successfully performed an arterial switch operation and coronary transfer by tube graft reconstruction with autologous aortic tissue to treat the dextro-transposition of the great arteries and atrial septal defect with a single-sinus origin of the coronary arteries.

셀 전송비율에 의한 우선순위 제어방식을 사용한 ATM 스위치의 성능 분석 (Performance Analysis of ATM Switch Using Priority Control by Cell Transfer Ratio)

  • 박원기;김영선;최형진
    • 전자공학회논문지A
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    • 제32A권12호
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    • pp.9-24
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    • 1995
  • In this paper, we proposed and analysed two kinds of priority control mechanism to archive the cell loss rate requirement and the delay requirement of each class. The service classes of our concern are the high time priority class(class 1) and the high loss priority class(class 2). Two kinds of priority control mechanism is divided by the method of storing the arriving class 2 cell in buffer on case of buffer full. The first one is the method which discarding the arriving class 2 cell, the second one is the mothod which storing the arriving class 2 cell on behalf of pushing out the class 1 cell in buffer. In the proposed priority schemes, one cell of the class 1 is transmitted whenever the maximum K cells of the class 2 is transmitted on case of transmitting the class 1 cell and the class 2 cell sequentially. In this paper, we analysed the cell loss rate and the mean cell delay for each class of the proposed priority scheme by using the Markov chain. The analytical results show that the characteristic of the mean cell delay becomes better for the class 1 cell and that of the cell loss rate becomes better for the class 2 cell by selecting properly the cell transfer ratio according to the condition of input traffic.

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고속라우터에 대한 고찰(I)-STC104의 레이블링 알고리즘 (Study on High Speed Routers(I)-Labeling Algorithms for STC104)

  • 이효종
    • 정보처리학회논문지A
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    • 제8A권2호
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    • pp.147-156
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    • 2001
  • A high performance routing switch is an essential device to either the high performance parallel processing or communication networks that handle multimedia transfer systems such as VOD. The high performance routing chip called STC104 is a typical example in the technical aspect which has 32 bidirectional links of 100Mbps transfer sped. It has exploited new technologies, such as wormhole routing, interval labeling, and adaptive routing method. The high speed router has been applied into some parallel processing system as a single chip. However, its performance over the various interconnection networks with multiple routing chips has not been studied. In this paper, the strucrtures and characteristics of the STC104 have been investigated in order to evaluate the high speed router. Various topology of the STC104, such as meshes, torus, and N-cube are defined and constructed. Algorithms of packet transmission have been proposed based on the interval labeling and the group adaptive routing method implemented in the interconnected network. Multicast algorithms, which are often requited to the processor networks and broadcasting systems, modified from U-mesh and U-torus algorithms have also been proposed overcoming the problems of point-to-point communication.

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2단 역률보상회로를 구성하는 Interleaved 승압형 컨버터의 해석 및 설계 (Analysis and Design of Interleaved Boost Power Factor Corrector on Two Stage AC/DC PFC Converter)

  • 허태원;손영대;김동완;김춘삼;박한석;우정인
    • 대한전기학회논문지:전기기기및에너지변환시스템부문B
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    • 제52권7호
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    • pp.343-351
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    • 2003
  • In this paper, interleaved boost converter is applied as a first-stage converter in switch mode power supply. The first-stage converter plays a role to improve power factor. Interleaved Boost Power Factor Corrector(IBPFC) can reduce input current ripple as a single voltage control loop only without inner current loop, because input current is divided each 50% by two switching devices. Each converter cell is also operated in discontinuous current mode and inductor current of each converter is discontinuous. Total input current which is composed by each converter cell is continuous current. Thus, IBPFC is able to improve input current ripple. IBPFC operating in discontinuous current mode can be classified as six modes from switching state and be carried out state space averaging small signal modeling. A control transfer function is obtained according to the modeling. Not only steady-state characteristics but also dynamic characteristics is considered. Single voltage control loop is also constructed by the control transfer function. From experimental result, improvement of power factor and input current ripple are verified.

A Study on the Effects of SMVEs Export Modes on Export Amount and Period

  • Coo, Byung-Mo
    • 산경연구논집
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    • 제9권1호
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    • pp.39-49
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    • 2018
  • Purpose - This present aims to analyze the effect of export modes on initial export amount and time to export by selecting export modes among various success strategies and factors. Research design, data, and methodology - It surveyed 980 small and mid-sized venture enterprises across Korea. The export modes and its impact on exports through frequency analysis and cross analysis, and validated through a PPML(regression analysis applied the enterprise growth model) analysis. Results - Five export modes were investigated : direct export, indirect export, transfer from direct export to indirect export, transfer from direct export to indirect export, and parallel export to indirect export. It was found that SMVEs that exported directly from establishment to initial export had the shortest period, and also had the highest export price Conclusions - From a marketing point of view, it took an average of 1.6 years to switch from export directly to indirect export or directly export, and the reason for the export modes conversion was to supplement export specialists and improve export competitiveness. And the export amount and time period that SMVEs establishes and export is a significant factor in export success strategy and there has been few prior study in export modes.

출력포트 확장 방식을 사용한 입출력 버퍼형 ATM 교환기에서의 성능 비교 분석 (Performance Analysis of Input-Output Buffering ATM Switch with Output-port Expansion Mechanism)

  • 권세동;박현민
    • 정보처리학회논문지C
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    • 제9C권4호
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    • pp.531-542
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    • 2002
  • 입력과 출력에 버퍼를 갖는 ATM 교환기의 셀 폐기 방법은 기존의 귀환(Backpressure)모드와 손실(Queueloss)모드가 있으며, 최근에는 두 모드의 단점을 보완한 하이브리드(Hybrid)모드가 제안되었다. 하이브리드모드는 목적하는 출력 버퍼와 입력 버퍼가 모두 포화일 경우에만 셀을 폐기하는 방식이다. 본 논문에서는 유니폼 트래픽하에서 Output-port expansion 기법을 사용한 귀환 손실 모드 및 하이브리드모드 하에서의 셀 손실률과 셀 지연을 성능 비교 분석한다 Output-port expansion 기법은, 한 타임 슬롯동안에 입력포트 당 하나의 셀만 교환되며, 만약 하나 이상의 셀들이 같은 출력포트로 향하고자 하면, 최대 교환되는 셀 수를 K(Output-port expansion ratio)개로 제한하는 방식이다. 셀 손실률을 비교 분석한 결과, 이전의 연구에서와는 달리 로드 0.9를 기점으로. 0.9이하의 로드에서는 하이브리드 모드가, 0.9 이상의 로드에서는 손실모드가 가장 낮은 셀 손실률을 보인다. 셀 지연을 비교 분석한 결과, 한 개의 교환기 성능 분석에서는 셀 손실로 인한 재전송(retransmission)을 고려하지 않는 관계로, 예상한 바와 같이, 로드가 많아질수록 셀 손실률이 높은 귀환모드가 K를 높일수록 다른 모드에 비해 낮은 셀 지연을 보였다.

SPDT 단일고주파집적회로 스위치용 pHEMT 채널구조 설계 (Design of pHEMT channel structure for single-pole-double-throw MMIC switches)

  • 문재경;임종원;장우진;지흥구;안호균;김해천;박종욱
    • 한국진공학회지
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    • 제14권4호
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    • pp.207-214
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    • 2005
  • 본 연구에서는 스위치, 위상변위기, 감쇄기등 전파제어회로를 설계 및 제작할 수 있는 pHEMT스위치 소자에 적합한 에피구조를 설계하였다. 고성능의 스위치 소자를 위한 pHEMT 채널층 구조는 이중 면도핑층을 가지며 사용 중 게이트 전극의 전계강도가 약한 깊은 쪽 채널층의 Si 면농도가 상층부보다 약 1/4정도 낮을 경우 격리도등 우수한 특성을 보였다. 설계된 에피구조와 ETRI의 $0.5\mu$m pHEMT MMIC 공정을 이용하여 2.4GHz 및 5GHz 대역 표준 무선랜 단말기에 활용 가능한 SPDT Tx/Rx MMIC 스위치를 설계 및 제작하였다. 제작된 SPDT형 스위치는 주파수 6.0 GHz, 동작전압 0/-3V에서 삽입손실 0.849 dB, 격리도 32.638 dB, 그리고 반사손실 11.006 dB의 특성을 보였으며, 전력전송능력인 $P\_{1dB}$는 약 25dBm, 그리고 선형성의 척도인 IIP3는 42 dBm 이상으로 평가되었다. 이와 같은 칩의 성능은 본 연구에서 개발된 SPDT 단일고주파집적회로 스위치가 2.4GHz뿐만 아니라 SGHB 대역 무선랜 단말기에 활용이 충분히 가능함을 말해준다.

The Study of Single Phase Source Stability consider for The DSC Cell's Operation Character by Controlled Feed-back Circuit

  • Lee, Hee-Chang
    • Journal of information and communication convergence engineering
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    • 제4권4호
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    • pp.170-173
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    • 2006
  • Recently, with increasing efficiency of DSC (photo-electrochemical using a nano-particle), The Performance of DSC solar generation system also needs improvement. The approach consists of a Fly-back DC-DC (transfer ratio 1:10) converter to boost the DSC cell voltage to 300VDC. The four switch (MOSFET) inverter is employed to produce 220V, 60Hz AC outputs. High performance, easy manufacturability, lower component count., safety and cost are addressed. Protection and diagnostic features form an important part of the design. Another highlight of the proposed design is the control strategy, which allows the inverter to adapt to the: requirements of the load as well as the power source. A unique aspect of the design is the use of the DSP TMS320LF2406 to control the inverter by current and voltage feed-back. Efficient and smooth control of the: power drawn from the DSC Cell is achieved by controlling the front end DC-DC converter in current mode.

A Study on the Design of a Pulse-Width Modulation DC/DC Power Converter

  • Lho, Young-Hwan
    • International Journal of Aeronautical and Space Sciences
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    • 제11권3호
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    • pp.201-205
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    • 2010
  • DC/DC Switching power converters are commonly used to generate regulated DC output voltages with high-power efficiencies from different DC input sources. A switching converter utilizes one or more energy storage elements such as capacitors, or transformers to efficiently transfer energy from the input to the output at periodic intervals. The fundamental boost converter studied here consists of a power metal-oxide semiconductor field effect transistor switch, an inductor, a capacitor, a diode, and a pulse-width modulation circuit with oscillator, amplifier, and comparator. A buck converter containing a switched-mode power supply is also studied. In this paper, the electrical characteristics of DC/DC power converters are simulated by simulation program with integrated circuit emphasis (SPICE). Furthermore, power efficiency was analyzed based on the specifications of each component.

SPICE를 이용한 ACRDCL 인버터의 시뮬레이션 및 설계 (Simulation and Design of ACRDCL Inverter Using SPICE)

  • 한수빈;정봉만;김규덕;최수현
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1994년도 하계학술대회 논문집 A
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    • pp.435-437
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    • 1994
  • Cramped resonant DC link inverter is analyzed by widely available software such as SPICE. In this paper, the model of ACRDCL which is based on converter switch function rather than actual circuit configuration is used. Power circuit is modeled by functional transfer function and the controller is based on the macro-model. Computer memory and runtime are based reduced compared to micro-model. Overall performance including control strategy and harmonic characteristics in the steady state can be analyzed easily.

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