• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.2151-2154
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• 2003

Internet is deeply rooted in everyday life and many things are performed using internet in real-world, therefore internet users increased because of convenience. Also internet accident is on the increase rapidly. The security vendor developed security system to protect network and system from intruder. Many hackings can be prevented and detected by using these security solutions. However, the new hacking methods and tools that can detour or defeat these solutions have been emerging and even script kids using these methods and tools can easily hack the systems. In consequence, system has gone through various difficulties. So, Necessity of intruder trace-back technology is increased gradually. Trace-back technology is tracing back a malicious hacker to his real location. trace-back technology is largely divided into TCP connection trace-back and IP packet trace-back to trace spoofed IP of form denial-of-service attacks. TCP connection trace-back technology that autonomously traces back the real location of hacker who attacks system using stepping stone at real time. In this paper, We will describe watermark trace-back system using TCP hijacking technique to supplement difficult problem of connection maintenance happened at watermark insertion. Through proposed result, we may search attacker's real location which attempt attack through multiple connection by real time.

• The KIPS Transactions:PartA
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• v.12A no.1 s.91
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• pp.1-6
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• 2005

This paper presents a new algorithm on low power survivor path memory implementation of the trace-back systolic array Viterbi algorithm. A novel idea is to reuse the already-generated trace-back routes to reduce the number of trace-back operations. And the spurious switching activity of the trace-back unit is reduced by making use of a clock gating method. Using the SYNOPSYS power estimation tool, DesignPower, our experimental result shows the average $40{\%}$ power reduction and $23{\%}$ area increase against the trace-back unit introduced in [1].

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.36-44
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• 2003

This paper proposes a Viterbi decoding scheme without trace-back operations to reduce the amount of memory storing the survivor path information, and to increase the decoding speed. The proposed decoding scheme is a modified register exchange scheme, and is verified by a simulation to give the same results as those of the conventional decoders. It is compared with the conventional decoding schemes such as the trace-back and the register exchange scheme. The memory size of the proposed scheme is reduced to 1/(5 x constraint length) of that of the register exchange scheme, and the throughput is doubled compared with that of the trace-back scheme. A decoder with a code rate of 2/3, a constraint length, K＝3 and a trace-back depth of 15 is designed using VHDL and implemented in an FPGA. It is also shown that the modified register exchange scheme can be applied to a block decoding scheme.

• Convergence Security Journal
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• v.14 no.2
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• pp.57-63
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• 2014

Internet users drastically increases, also through the Internet to buy various intrusion significantly increased. These various methods of intrusion defense thinking hacker attempting to hack the actual position of the real-time tracking of the intruder backtracking technique for research have been actively carried out. In this paper, a technique used in TCP Connection trace-back System in one packet trace-back technique watermarking technique using TCP Hijacking Connection Reply packets how to solve the difficulties of maintaining presented.

• Journal of KIISE:Information Networking
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• v.32 no.1
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• pp.1-11
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• 2005

Internet has become an essential part of our daily lives. Many of the day to day activities can already be carried out over Internet, and its convenience has greatly increased the number of Internet users. Hut as Internet gains its popularity, the illicit incidents over Internet has also proliferated. The intruder trace-back technology is the one that enables real time tracking the position of the hacker who attempts to invade the system through the various bypass routes. In this paper, the RTS algorithm which is the TCP connection trace-back system using the watermarking technology on Internet is proposed. Furthermore, the trace-bark elements are modeled by analyzing the Proposed trace-back algorithm, and the results of the simulation under the virtual topology network using ns-2, the network simulation tool are presented.

• ETRI Journal
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• v.26 no.1
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• pp.21-26
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• 2004

This paper proposes a new architecture for a Viterbi decoder with an efficient memory management scheme. The trace-back operation is eliminated in the architecture and the memory storing intermediate decision information can be removed. The elimination of the trace-back operation also reduces the number of operation cycles needed to determine decision bits. The memory size of the proposed scheme is reduced to 1/($5{\times}$ constraint length) of that of the register exchange scheme, and the throughput is increased up to twice that of the trace-back scheme. A Viterbi decoder complying with the IS-95 reverse link specification is designed to verify the proposed architecture. The decoder has a code rate of 1/3, a constraint length of 9, and a trace-forward depth of 45.

• The Journal of Society for e-Business Studies
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• v.22 no.4
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• pp.129-139
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• 2017

With the advent of FinTech, many financial services have become available in the mobile Internet environment and recently, there is an internet bank that provides all bank services online. As the proportion of financial services over the Internet increases, it offers convenience to users, but at the same time, the threat of financial network is increasing. Financial institutions are investing heavily in security systems in case of an intrusion. However attacks by hackers are getting more sophisticated and difficult to cope with. However, applying an IP Trace-back method that can detect the actual location of an attacker to a financial network can prepare for an attacker's arrest and additional attacks. In this paper, we investigate IP Trace-back technology that can detect the actual location of attacker and analyze it to apply it to financial network. And we propose a new IP Trace-back method through Infra-structure construction through simulation experiments.

• Journal of Environmental Health Sciences
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• v.21 no.3
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• pp.96-101
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• 1995

A selective and highly sensitive spectrophotometric measurements have been developed for the determination of trace mercury(II) with thiosulfate and PAR. Hg(II)-thiosulfate complex was extracted into high molecular alkylamine such as quaternary ammonium salt and back extracted into 1 M-HCl solution. The Hg(II)-PAR complex has maximum absorbance at 499 nm and obeys Beer's law in the range of 0.04~1.0 $\mu g/mL$ of mercury(II). The molar absorptivity and Sandell's sensitivity are $6.27\times 10^4 L.mole^{-1} cm^{-1}$ and $3.2\times 10^{-3}g/cm^2$ respectively.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3199-3201
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• 1999

Convolutional coding with Viterbi decoding is known as a powerful method for forward error correction among many kinds of channel coding methods. This paper presents a soft decision Viterbi decoder which has systolic array trace-back architecture[1]. Soft decision is known as more effective method than hard decision and most of digital communication systems use soft decision. The advantage of using a systolic array decoder is that the trace-back operation can be accomplished continuously in an array of registers in a pipe-line fashion, instead of waiting for the entire trace-back procedure to be completed at each iteration. Therefore it may be suitable for faster communication system. We described operations of each module of the decoder and showed results of the logic synthesis and functional simulation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.3
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• pp.24-31
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• 1998

This paper presents a pipeline high-level synthesis tool for designing trace-back systolic array viterbi decoder. It consists of a dta flow graph(DFG) generator and a pipeline data path synthesis tool. First, the DFG of the vitrebi decoder is generated in the from of VHDL netlist. The inputs to the DFG generator are parameters of the convolution encoder. Next, the pipeline scheduling and allocationare performed. The synthesis tool explores the design space efficiently, synthesizes various designs which meet the given constraints, and choose the best one.