• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.10
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• pp.93-100
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• 2013

Generally, the conventional battery charging system using an analog method has the large, heavy hardware and low efficiency. Also, it has the disadvantage that it is necessary to replace the control circuit on the basis of the characteristic curve of the specific battery cell. The proposed programmable digital LLC resonant charging system use high efficiency control system(CC-CV), and has characteristic a small hardware and advantage that a digital programming of the voltage, current, and battery capacity characteristics can be flexible. The system proposed the use of Half-bridge LLC resonant converter is possible to improve efficiency and reduce switching losses by using ZVS topology. Further, a constant voltage - constant current(CC-CV) control algorithm apply to the charger which using a buck converter. The performance of the proposed system is demonstrated through experiments.

• Journal of Power Electronics
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• v.16 no.2
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• pp.786-797
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• 2016

This paper describes the design and development of a novel semiconductor-based solid-state switch for damped oscillating voltage test system. The proposed switch is configured as two identical series-connected switch stacks, each of which comprising 10 series-connected IGBT function units. Each unit consists of one IGBT, a gate driver, and an auxiliary voltage sharing circuit. A single switch stack can block 20 kV-rated high voltage, and two stacks in series are proven applicable to 30 kV-rated high voltage. The turn-on speed of the switch is approximately 250 ns. A flyback topology-based power supply system with a front-end power factor correction is built for the drive circuit by loosely inductively coupling each unit with a ferrite core to the primary side of a power generator to obtain the advantages of galvanic isolation and compact size. After the simulation, measurement, and estimation of the parasitic effect on the gate driver, a prototype is assembled and tested under different operating regimes. Experimental results are presented to demonstrate the performance of the developed prototype.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.2
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• pp.542-558
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• 2016

Vehicular Ad Hoc Networks (VANETs) are self-configuring networks where the nodes are vehicles equipped with wireless communication technologies. In such networks, limitation of signal coverage and fast topology changes impose difficulties to the proper functioning of the routing protocols. Traditional Mobile Ad Hoc Networks (MANET) routing protocols lose their performance, when communicating between vehicles, compromising information exchange. Obviously, most applications critically rely on routing protocols. Thus, in this work, we propose a methodology for investigating the performance of well-established protocols for MANETs in the VANET arena and, at the same time, we introduce a routing protocol, called Genetic Network Protocol (G-NET). It is based in part on Dynamic Source Routing Protocol (DSR) and on the use of Genetic Algorithms (GAs) for maintenance and route optimization. As G-NET update routes periodically, this work investigates its performance compared to DSR and Ad Hoc on demand Distance Vector (AODV). For more realistic simulation of vehicle movement in urban environments, an analysis was performed by using the VanetMobiSim mobility generator and the Network Simulator (NS-3). Experiments were conducted with different number of vehicles and the results show that, despite the increased routing overhead with respect to DSR, G-NET is better than AODV and provides comparable data delivery rate to the other protocols in the analyzed scenarios.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.238-246
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• 2011

A 3-5 GHz UWB radar chip in 0.13 ${\mu}m$ CMOS process is presented in this paper. The UWB radar transceiver for surveillance and biometric applications adopts the equivalent time sampling architecture and 4-channel time interleaved samplers to relax the impractical sampling frequency and enhance the overall scanning time. The RF front end (RFFE) includes the wideband LNA and 4-way RF power splitter, and the analog signal processing part consists of the high speed track & hold (T&H) / sample & hold (S&H) and integrator. The interleaved timing clocks are generated using a delay locked loop. The UWB transmitter employs the digitally synthesized topology. The measured NF of RFFE is 9.5 dB in 3-5 GHz. And DLL timing resolution is 50 ps. The measured spectrum of UWB transmitter shows the center frequency within 3-5 GHz satisfying the FCC spectrum mask. The power consumption of receiver and transmitter are 106.5 mW and 57 mW at 1.5 V supply, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.1-10
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• 2010

This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to $V_{dd}$. It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. 2PASCL has switching activity that is lower than dynamic logic. We also design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology. From the simulation results, we find that 2PASCL 4-inverter chain logic can save up to 79% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 1 to 100 MHz. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

• Journal of Power Electronics
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• v.15 no.4
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• pp.899-909
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• 2015

A dual-input boost-buck converter with coupled inductors (DIBBC-CI) is proposed as a thermoelectric generator (TEG) power conditioner with a wide input voltage range. The DIBBC-CI is built by cascading two boost cells and a buck cell with shared inverse coupled filter inductors. Low current ripple on both sides of the TEG and the battery are achieved. Reduced size and power losses of the filter inductors are benefited from the DC magnetic flux cancellation in the inductor core, leading to high efficiency and high power density. The operational principle, impact of coupled inductors, and design considerations for the proposed converter are analyzed in detail. Distributed maximum power point tracking, battery charging, and output control are implemented using a competitive logic to ensure seamless switching among operational modes. Both the simulation and experimental results verify the feasibility of the proposed topology and control.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.399-400
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• 2012

The proposed battery charger presented in this paper is suitable for Lead-Acid Battery and the dc/dc buck converter topology is applied as a charger circuit. The technique adopted in this charger is constant current & constant voltage dual mode, which is decided by the value of voltage of proposed battery. Automatic mode change function is detected by the percentage value of level of battery charging. CC Mode (Constant Current Mode) is operated when charging level is below 80% of the total charging of Battery voltage and above 80% of battery voltage charging, CV Mode (Constant Voltage Mode) is automatically operated. As the charging level exceeds 120%, it automatically terminates charging. The feedback signal to the PWM generator for charging the battery is controlled by using the current and voltage measurement circuits simultaneously. This technique will degrade the damage of proposed type of battery and improve the power efficiency of charger. Finally, a prototype charger circuit designed for a 12-V 7-Ah lead acid battery is constructed and tested to confirm the theoretical predictions. Satisfactory performance is obtained from simulation and the experimental results.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.3
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• pp.1213-1237
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• 2019

Vehicular Ad-hoc Network (VANET) facilities envision future Intelligent Transporting Systems (ITSs) by providing inter-vehicle communication for metrics such as road surveillance, traffic information, and road condition. In recent years, vehicle manufacturers, researchers and academicians have devoted significant attention to vehicular communication technology because of its highly dynamic connectivity and self-organized, decentralized networking characteristics. However, due to VANET's high mobility, dynamic network topology and low communication coverage, dissemination of large data packets (e.g. multimedia content) is challenging. Clustering enhances network performance by maintaining communication link stability, sharing network resources and efficiently using bandwidth among nodes. This paper proposes a mobility-based, multi-hop clustering algorithm, (MBCA) for multimedia content broadcasting over an IEEE 802.11p-LTE-enabled hybrid VANET architecture. The OMNeT++ network simulator and a SUMO traffic generator are used to simulate a network scenario. The simulation results indicate that the proposed clustering algorithm over a hybrid VANET architecture improves the overall network stability and performance, resulting in an overall 20% increased cluster head duration, 20% increased cluster member duration, lower cluster overhead, 15% improved data packet delivery ratio and lower network delay from the referenced schemes [46], [47] and [50] during multimedia content dissemination over VANET.

• Journal of Power Electronics
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• v.14 no.2
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• pp.271-281
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• 2014

Fluctuating wind conditions necessitate the use of a variable speed wind turbine (VSWT) with a AC/DC/AC converter scheme in order to harvest the maximum power from the wind and to decouple the synchronous generator voltage and frequency from the grid voltage and frequency. In this paper, a combination of a three phase diode bridge rectifier (DBR) and a modified topology of the diode clamped multilevel inverter (DCMLI) has been considered as an AC/DC/AC converter. A control strategy has been proposed for the DCMLI to achieve the objective of grid interface of a wind power system together with local load compensation. A novel fixed frequency current control method is proposed for the DCMLI based on the level shifted multi carrier PWM for achieving the required control objectives with equal and uniform switching frequency operation for better control and thermal management with the modified DCMLI. The condition of the controller gain is derived to ensure the operation of the DCMLI at the fixed frequency of the carrier. The converter current injected into the distribution grid is controlled in accordance with the wind power availability. In addition, load compensation is performed as an added facility in order to free the source currents being fed from the grid of harmonic distortion, unbalance and a low power factor even though the load may be unbalanced, non-linear and of a poor power factor. The results are validated using PSCAD/EMTDC simulation studies.

• Journal of Power Electronics
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• v.18 no.2
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• pp.547-557
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• 2018

This work proposes a control method of frequency stabilization for grid integration of large-scale wind farms via the voltage source converter-based high-voltage direct current (VSC-HVDC) technology. First, the topology of grid integration of a large-scale wind farm via the VSC-HVDC link is provided, and simple control strategies for wind turbines, wind farm side VSC (WFVSC), and grid side VSC are presented. Second, a mathematical model between the phase angle of WFVSC and the frequency of the wind farm is established. The control principle of the large-scale wind power integrated system is analyzed in theory in accordance with the mathematical model. Third, frequency and AC voltage controllers of WFVSC are designed based on the mathematical model of the relationships between the phase angle of WFVSC and the frequency of the wind farm, and between the modulation index of WFVSC and the voltage of the wind farm. Corresponding controller structures are established by deriving a transfer function, and an optimization method for selecting the parameters of the frequency controller is presented. Finally, a case study is performed under different operating conditions by using the DIgSILENT/PowerFactory software. Results show that the proposed control method has good performance in the frequency stabilization of the large-scale wind power integrated system via the VSC-HVDC technology.