• Journal of Advanced Navigation Technology
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• v.7 no.2
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• pp.141-148
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• 2003

This paper presents and compares several techniques that detect the symbol rate of unknown received signal. Symbol rate is detected from the power spectral density of the circuits such as the delay and multiplier circuit, the square law circuit, and analytic signal, etc. As a result of discrete Fourier transform of the output signals of these circuits, a lot of spectral lines and some peaks appear in frequency domain and the position of first peak is corresponding to the symbol rate. If a spectral line on the frequency that is not located in symbol rate is larger than the first peak, the symbol rate is erroneously detected. Thus, the ratio between the value of first peak and the highest side spectral line is used for the measure of the performance of symbol rate detector. For the MPSK modulation, the analytic signal method shows better performance than the delay and multiplier and square law circuits when the received signal power is lager than -20dB. It is also noted that the delay and multiplier circuit is not able to detect the symbol rate for the QAM modulation.

• Journal of Korea Society of Industrial Information Systems
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• v.8 no.1
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• pp.83-91
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• 2003

High-speed QPSK demodulator has been in important design objective of any wireless communication systems, especially those offering broadband multimedia service. This paper describes all-digital QPSK demodulator for high-speed wireless communications, and its hardware structures are discussed. All-digital QPSK demodulator is mainly composed of symbol time circuit and carrier recovery circuit to estimate timing and phase-offsets. There are various schemes. Among them, we use Gardner algorithm and Decision-Directed carrier recovery algorithm which is most efficient scheme to warrant the fast acquisition and tacking to fabricate FPGA chip. The testing results of the implemented onto CPLD-EPF10K100GC 503-4 chip show demodulation speed is reached up to 2.6[Mbps]. If it is implemented a CPLD chip with speed grade 1, the demodulation speed can be faster by about 5 times. Actually in case of designing by ASIC, its speed my be faster than CPLD by 5 times. Therefore, it is possible to fabricate the all-digital QPSK demodulator chipset with speed of 50[Mbps].

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.880-883
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• 2002

In this paper, we propose the synchronization recovery algorithm which is suitable to wireless multimedia of wireless channel situation which is being used OFDM signaling method. The basic of the suggested clock synchronization. restoration Algorithm is to getting the shock response of channel or getting the multipath strength profile through IFFT after the getting the frequency, response of deducted channel from channel deductor of receiver and to trace the location in the channel energy concentrated area of timing area. And it also analysis the start point of 64-QAM and 16-QAM if the sampling clock offset has the sample of $\pm$1-3, and we identified the occurance of performance deterioration when occures more than 2 samples of offset to compare with star point and BER performance in optimum sampling point result of BER performance checking, and we know that the recovery algorithm proposed algorithm also provide excellent synchronization characteries under frequency, selecting fading channel as result of simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.9A
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• pp.1332-1339
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• 2000

This paper presents the architecture and design of a high speed asymmetric data transmission baseband MODEM ASIC chip for CATV networks. The implemented MODEM chip supports the physical layer of the DOCSIS(Data Over Cable Service Interface Specification) standard in MCNS(Multimedia Cable Network System) The chip consists of a QPSK/16-QAM transmitter and a 64/256-QAM receiver which contain a symbol timing recovery circuit, a carrier recovery circuit, a blind equalizer using MMA and LMS algorithms. The chip can support data rates of 64Mbps at 256 QAM and 48Mbps at 64-QAM and can provide symbol rates up to 8MBaud. This symbol rate is faster than existing QAM receivers. We have performed logic synthesis using the $0.35\mu\textrm{m}$ standard cell library. The total number of gates is about 290,000 and the implemented chip is being fabricated and will be delivered soon.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.246-249
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• 2004

The purpose of this study was to investigate the characteristics between EMG timing of muscle contraction and motor impairment in chronic hemiplegic stroke patients. Delay time and co-contraction of 4 patients who had stroke less than 3 years were measured during isometric wrist flexion and extension along the 3 seconds beep signal. Onset and offset of muscle contraction were significantly delayed on the more affected sides than control sides. Offset was significantly delayed than the onset on the affected sides in wrist flexion. Also, recruitment of antagonist was larger than agonist on the affected sides. Co-contraction ratio on the affected side was significantly smaller than control sides in wrist flexion. In affected sides, Fugl-Meyer motor assessment(FMA) shows the correlation of onset delay in wrist flexion and extension. However, co-contraction ratio correlated with FMA in wrist flexion. EMG assessment is likely to be useful outcome measure and provide insights into mechanism for motor recovery in stroke patients.

• Nuclear Engineering and Technology
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• v.47 no.4
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• pp.443-453
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• 2015

A hybrid safety injection tank (H-SIT) can enhance the capability of an advanced power reactor plus (APR+) during a station black out (SBO) that is accompanied by a severe accident. It may a useful alternative to an electric motor. The operations strategy of the H-SIT has to be investigated to achieve maximum utilization of its function. In this study, the master logic diagram (i.e., an analysis for identifying the differences between an H-SIT and a safety injection pump) and an accident case classification were used to determine the parameters of the H-SIT operation. The conditions that require the use of an H-SIT were determined using a decision-making process. The proper timing for using an H-SIT was also analyzed by using the Multi-dimensional Analysis of Reactor Safety (MARS) 1.3 code (Korea Atomic Energy Research Institute, Daejeon, South Korea). The operation strategy analysis indicates that a H-SIT can mitigate five types of failure: (1) failure of the safety injection pump, (2) failure of the passive auxiliary feedwater system, (3) failure of the depressurization system, (4) failure of the shutdown cooling pump (SCP), and (5) failure of the recirculation system. The results of the MARS code demonstrate that the time allowed for recovery can be extended when using an H-SIT, compared with the same situation in which an H-SIT is not used. Based on the results, the use of an H-SIT is recommended, especially after the pilot-operated safety relief valve (POSRV) is opened.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.4C
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• pp.364-370
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• 2006

It is required for correct signal detection to accurately maintain the synchronization of frequency and timing in a TDMA system. In this paper, we consider nondecision-aided estimation of frequency offset for the transmission of QPSK signal in a TDMA-based satellite system. The proposed scheme estimates the phases of two parts in the burst and then estimates the frequency offset based on the difference between the two estimated phases. Thus, it can provides performance comparable to that of conventional schemes, while significantly reducing the implementation complexity, The performance of the proposed scheme is analyzed and verified by computer simulation, when applied to a GSM based geostationary earth orbit mobile radio(GMR) system.

• Journal of Biomedical Engineering Research
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• v.24 no.5
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• pp.435-442
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• 2003

In this paper, biomechanical aspects of dynamic대학교postural responses against forward perturbations were experimentally determined simultaneous measurements of joint angles, accelerations. EMG activations, center of pressure(CoP) movements and ground reaction forces(GRF), Thirteen young healthy volunteers, stood on a flat platform, were translated into the forward direction by an AC servo-motor at two separate velocities(0.1m and 0.2m/s). In order to recover postural balance against the forward perturbation, joint motions were observed in the sequence of the ankle dorsiflexion, the knee flexion and then the hip flexion during the later acceleration phase. Both acceleration patterns at the heel and the sacrum were shown the forward acceleration pattern during the later acceleration phase and early of constant velocity phase as increasing platform velocity, respectively. Tibialis anterior(TA) for the ankle dorsiflexion and biceps femoris(BF) for the knee flexion. the primary muscle to recover the forward perturbation, was activated during the half of acceleration phase. Ankle strategy was used for slow-velocity perturbation, but mixed strategy of both ankle and hip used for the fast-velocity perturbation. In addition, parameters of perturbation such as timing and magnitude influenced the postural response against the perturbation.

• Transactions of the Korean Society of Automotive Engineers
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• v.8 no.5
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• pp.129-137
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• 2000

The powertrain is an important factor for the interior and exterior noise behavior of the vehicle Thus, the noise vibration and harshness(NVH) behavior of an engine is becoming a major target of the powertrain development. This paper describes the analyses with the aim to reduce the vibration and noise of an advanced inline 4-cylinder diesel engine block by use of CAE methods. The characteristics of an engine block as a main excitation source of car interior noise is studied. Particularly, The effect of balance shaft to reduce the 2nd order engine excitation force is calculated by forced vibration and radiated noise analysis. The engine exitation forces are obtained under real operating conditions. It is shown that the reduction of vibration and noise level by adapting blancing shaft is well predicted and rediated noise is directly related to the surface velocity of engine block.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.3
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• pp.14-21
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• 1989

In the digital transmission equipment, the input jitter tolerance is a function of input timing recovery circuit characteristics. Especially, in the asynchronous multiplexers, it is also a function of the frame format, the buffer sizes in the synchronizer and desynchronizer, the PLL transfer function, and operating range of VCO in PLL In this paper, a new algorithm for calculating the jitter tolerance of the saynchronous digital transmission equipment is presented. With the new algorithm, we analyzed how the above factors limit the jitter tolerance in the equipment. We also measured the input jitter tolerance for a 45M-140M multiplexing equipment, whose results show the same trend with calculated tolerance.