• Journal of IKEEE
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• v.23 no.2
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• pp.681-686
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• 2019

This paper proposes a CMOS temperature sensor using inverter delay chains of the same size based on the pulse shrinking method. A temperature-pulse converter (TPC) uses two different temperature delay lines with inverter chains to generate a pulse in proportion to temperature, and a time-digital converter (TDC) shrinks the pulse using inverter chains of the same size to convert pulse width into a digital value to be insensitive to process changes. The chip was implemented with a $0.49{\mu}m{\times}0.23{\mu}m$ area using a $0.35{\mu}m$ CMOS process with a supply voltage of 3.3V. The measurement results show a resolution of $0.24^{\circ}C/bit$ for 9-bit data for a temperature sensor range of $0^{\circ}C$ to $100^{\circ}C$.

• Journal of Power Electronics
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• v.14 no.5
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• pp.890-898
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• 2014

Critical conduction mode boost power factor correction converters operating at the boundary of continuous conduction mode and discontinuous conduction mode have been widely used for power applications lower than 300W. This paper proposes an enhanced variable on-time control method for the critical conduction mode boost PFC converter to improve the total harmonic distortion characteristic. The inductor current, which varies according to the input voltage, is analyzed in detail and the optimal on-time is obtained to minimize the total harmonic distortion with a digital controller using a TMS320F28335. The switch on-time varies according to the input voltage based on the computed optimal on-time. The performance of the proposed control method is verified by a 100W PFC converter. It is shown that the optimized on-time reduces the total harmonic distortion about 52% (from 10.48% to 5.5%) at 220V when compared to the variable on-time control method.

• Journal of Electrical Engineering and Technology
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• v.9 no.5
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• pp.1447-1453
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• 2014

This paper proposes the new method based on the availability of three points measurement and convexity of photovoltaic (PV) curve characteristic at the maximum power point (MPP). In general, the MPP tracking (MPPT) function is the important part of all PV systems due to their power-voltage (P-V) characteristics related with weather conditions. Then, the analog-to-digital converter (ADC) and low pass filter (LPF) are required to measure the voltage and current for MPPT by the digital controller, which is used to implement the PV power conditioning system (PCS). The measurement and quantization error due to rounding or truncation in ADC and the delay of LPF might degrade the reliability of MPPT. To overcome this limitation, the proposed method is proposed while improving the performances in both steady-state and dynamic responses based on the detailed investigation of its properties for availability and convexity. The performances of proposed method are evaluated with the several case studies by the PSCAD/EMTDC$^{(R)}$ simulation. Then, the experimental results are given to verify its feasibility in real-time.

• ETRI Journal
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• v.35 no.1
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• pp.109-119
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• 2013

Static testing of analog-to-digital (A/D) and digital-to-analog (D/A) converters becomes more difficult when they are embedded in a system on chip. Built-in self-test (BIST) reduces the need for external support for testing. This paper proposes a new static BIST structure for testing both A/D and D/A converters. By sharing test circuitry, the proposed BIST reduces the hardware overhead. Furthermore, test time can also be reduced using the simultaneous test strategy of the proposed BIST. The proposed method can be applied in various A/D and D/A converter resolutions and analog signal swing ranges. Simulation results are presented to validate the proposed method by showing how linearity errors are detected in different situations.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.667-670
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• 2004

In this paper, we have presented the improved IF transceiver architecture and the implementation and experimental results on re-configurable transceiver based on digital IF for multiple wideband OFDM/TDD base stations for high-speed portable internet-service in which is issued Korea. The implemented IF transceiver has been designed to support multiple frequency allocations and multiple standards by only modifying the programmable software not its hardware like as the software-defined-radio concept. Also, the digital complex quadrature modulation technique has been used for the digital IF transmitter, which is able to combine multiple frequency bands in digital processing block not RF block and to reject the image frequency signals. And the bandpass sampling technique has been used for the digital IF receiver to reduce the sampling rate of ADC. This paper has shown the experiment results on the frequency response and constellation on the base-station implemented using the modified IEEE 802.16a/e physical layer channel structure based on OFDM/TDD.

• Journal of Electrical Engineering and Technology
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• v.8 no.6
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• pp.1389-1399
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• 2013

A discrete controller is designed for low power dc-dc switched mode power supplies. The approach is based on time domain and the control loop continuously and concurrently tunes the compensator parameters to meet the converter specifications. A digital state feedback control combined with the load estimator provides a complete compensation, which further improves the dynamic performance of the closed loop system. Simulation of digitally controlled Buck converter is performed with MATLAB/Simulink. Experimental results are given to demonstrate the effectiveness of the controller using LabVIEW with a data acquisition card (model DAQ Pad - 6009).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1259-1264
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• 1999

In this paper, the High-speed, Low-power Analog-Digital Conversion Archecture is porposed using the Pipelined archecture for High-speed conversion rate and the Successive-Approximation archecture for Low-power consumption. This archecture is the Successive-Approximation archecture using Pipelined Comparator array to change reference voltage during Holding Time. The Analog-to-Digital Converter for video processing is designed using 0.8${\mu}{\textrm}{m}$ CMOS tchnology. When an 6-bit 10MS/s Analog-to-Digital Converter is simulatined, the INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 37dB at a sampling rate of 10MHz with 100KHz sine input signal. The power consumption is 1.46mW at 10MS/s. When an 8-bit 10MS/s Analog-to Digital Converter is simulatined, the INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 41dB at a sampling rate of 100MHz with 100KHz sine input signal. The power consumption is 4.14m W at 10MS/s.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.8
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• pp.665-670
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• 2014

In this paper, characteristics of a tidal current power generation system are analysis using power hardware-in-the-loop simulation (PHILS). A 10 kW motor generator set is connected to the real grid through a fabricated 10 kW back to back converter. A power control scheme is applied to the back to back converter. A 2 MW class tidal current turbine is modeled in real time digital simulator (RTDS). Generating voltage and current from the 10 kW PMSG is applied to a 2 MW class tidal current turbine in the RTDS using PHILS. The PHILS results depict the rotation speed, power coefficient, pitch angle, tip-speed ratio, and output power of tidal current turbine. The PHILS results in this paper can contribute to the increasing reliability and stability of the tidal current turbines connected to the grid using PHILS.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.2
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• pp.258-264
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• 2011

In this paper, we designed a frequency synthesizer with a low phase noise and fast lock time and excellent spurious characteristics using the offset-PLL(Phase Locked Loop) that is used in GSM(Global System for Mobile communications). The proposed frequency synthesizer has low phase noise using three times down conversion and third offset frequency of this synthesizer is created by DDS(Direct Digital Synthesizer) to have high frequency resolution. Also, this synthesizer has fast switching speed using DAC(Digital to Analog Converter). but phase noise degraded due to DAC. we improved performance using the DAC noise filter.

• Journal of Power Electronics
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• v.11 no.2
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• pp.156-162
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• 2011

The control loop time delay caused by sampling, the zero-order-holder effect and calculations is inevitable in the digital control of dc-dc switching converters. The time delay will limit the bandwidth of the control loop and therefore degrade the transient performance of digital systems. In this paper, the quantization time delay effects with different time delay values based on a generic second-order system are analyzed. The conclusion that the bandwidth of digital control is reduced by about 20% with a one cycle delay and by 50% with two cycles of delay in comparison with no time delay is obtained. To compensate the time delay and to increase the control loop bandwidth, a duty ratio predictive control scheme based on linear extrapolation is proposed. The compensation effect and a comparison of the load variation transient response characteristics with analogy control, conventional digital control and duty ratio predictive control with different time delay values are performed on a point-of-load Buck converter by simulations and experiments. It is shown that, using the proposed technique, the control loop bandwidth can be increased by 50% for a one cycle delay and 48.2% for two cycles of delay when compared to conventional digital control. Simulations and experimental results prove the validity of the conclusion of the quantization effects of the time delay and the proposed control scheme.