• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.671-672
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• 2011

Time to digital converter is designed. To obtain the digital signal from time information the analog delay element is used. Because the analog delay element shows more stable characteristics compared to the digital delay element in view point of process variation. The designed circuit has temperature stale characteristics when the range of operating temperature is from $-20^{\circ}C$ to $70^{\circ}C$. The circuit is simulated and confirmed by HSPICE.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.893-898
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• 2017

A TDC(Time-to-Digital Converter) of counter-type is designed by $0.18{\mu}mCMOS$process and the supply voltage is 1.5 volts. The converted error of maximum $T_{CK}$ is occurred by the time difference between the start signal and the clock when the period of clock is $T_{CK}$ in the conventional TDC. And the converted error of -$T_{CK}$ is occurred by the time difference between the stop signal and the clock. However in order to compensate the disadvantage of the conventional TDC the clock is generated within the TDC circuit and the clock is synchronized with the start and stop signals. In the designed TDC circuit the conversion error is not occurred by the difference between the start signal and the click and the magnitude of conversion error is reduced (1/2)$T_{CK}$ by the time difference between the stop signal and the clock.

• Nuclear Engineering and Technology
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• v.55 no.2
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• pp.484-492
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• 2023

Time-to-digital converters (TDCs) based on the tapped delay line (TDL) architecture have been widely used in various applications requiring a precise time measurement. However, the poor uniformity of the propagation delays in the TDL implemented on FPGA leads to bubble error and large nonlinearity of the TDC. The purpose of this study was to develop an advanced TDC architecture capable of minimizing the bubble errors and improving the linearity. To remove the bubble errors, the decimated delay line (DDL) architecture was implemented on the UltraScale + FPGA; meanwhile, to improve the linearity of the TDC, a histogram uniformization (HU) and multi-chain TDL (MCT) methods were developed and implemented on the FPGA. The integral nonlinearities (INLs) and differential nonlinearities (DNLs) of the plain TDCs with the 'HU method' (HU TDC) and with 'both HU and MCT methods' (HU-MCT TDC) were measured and compared to those of the TDC with 'DDL alone' (plain TDC). The linearity of HU-MCT TDC were superior to those of the plain TDC and HU TDC. The experiment results indicated that HU-MCT TDC developed in this study was useful for improving the linearity of the TDC, which allowed for high timing resolution to be achieved.

• Journal of Biomedical Engineering Research
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• v.7 no.2
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• pp.133-138
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• 1986

Abstract In a conventional digital sector scan system in the ultrasound medical imaging, the sampling space is in the polar coordinates while the display space is in the cartesian coordinates, which necessitates a coordinate transformation process resultion process resulting the overall system very complex and bulky. In this paper we propose a new architecture of the Digital-Scan-Converter (DSC) for the ultrasound sector scan system in which sampling space is the same as the display space, so the data are displayed as they are acquired without any interpola- tion process required. To implement the above real time DSC. two frequency synthesizes with very high switching time and a low-pass filter are required. The former determines the precise location of the data points and the latter fills the gap betw- een pixels in the horizontal direction.

• Journal of Advanced Marine Engineering and Technology
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• v.11 no.4
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• pp.41-49
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• 1987

Recently microcomputers have come into wide use in the field of control. They are used not only as monitors and or controllers in various plant control systems but also for Computer Aided Design of control systems. In this paper, authors propose a method to design the reduced order observers for the higher order systems and have digital simulation of time responses of the optimal state feedback control system using the maximum principle. And the real time optimal state feedback control system for the third order plant which is realized by an anolog computer is constructed by means of a microcomputer, A/D converter and D/A converter. Time responses of the real time control system are compared with those obtained by the digital simulation and their well coincedence is confirmed.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.156-164
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• 2014

In a delay line type of a time-to-digital converter implemented in Field Programmable Gate Array, the timing accuracy decreases for a longer carry chain. In this paper, we propose a structure that has a multi-phase clock and a state machine to check metastability; this would reduce the required length of the carry chain with the same time resolution. To reduce the errors caused by the time difference in the four delay lines associated with a four-phase clock, the proposed TDC generates a single input pulse from four phase clocks and uses a single delay line. Moreover, the state machine is designed to find the phase clock that is used to generate the single input pulse and determine the metastable state without a synchronizer. With the measurement range of 1 ms, the measured resolution was 22 ps, and the non-linearity was 25 ps.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1296-1297
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• 2011

This paper deals with a power-hardware-in-the loop simulation (PHILS) of permanent magnet synchronous generator (PMSG) type wind power generation system (WPGS) using a real hardware which consists of a motor generator set with motor drive, real time digital simulator (RTDS), and back-to-back converter. A digital signal processor (DSP) controls the back-to-back converter connected between the back-to-back converter and the RTDS. The proposed PHILS can effectively be applied to demonstrate the operational characteristics of PMSG type WPGS under grid connection.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1627-1633
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• 2018

A constant voltage AC-DC converter based on digital assistant technology is proposed in this paper, which has rapid dynamic response capability. The converter operates in the PFM (Pulse Frequency Modulation) mode. According to the load state, the compensation current produced by the digital compensation module was injected into the CS pin to adjust the switching pulse width dynamically and improve the dynamic response. The control chip is implemented based on NEC $1{\mu}m$ 5V/40V HVCMOS process. A 5V/1.2A prototype has been built to verify the proposed control method. When the load jumps from idle to heavy, the undershoot time is only 7.4ms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.39-46
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• 2005

A DC-DC converter with digital controller is realized. the digital controller has several advantages such as robustness, fast design time, and high flexibility. however, since the DC-DC output voltage is analog, an analog-to-digital conversion scheme is always essential in all digital controllers. A simple and efficient delta-sigma modulator is used as a conversion scheme in out implementation. The measurement results show good voltage regulation

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.2
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• pp.115-122
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• 2000

In design of a digital current controller for a 3cP PWM converter, its conventional model is used in obtaining i its discretized version. But, it has errors since the characteristics of SVPWM and time delay are not taken i into consideration. In this paper, the new reference frame model of a 3c~ PWJVI converter is proposed C considering these problems. Also, the direct digital current controller based on this model is designed without a any extra algolithm. A simple tuning algorithm for the proposed current controller is given to compensate the i inductaηce mismatch problem. Then simulation and experimental results show the validity of the algolithm.