• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.334-341
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• 2015

This research outlines the design of a HR-TDC (High Resolution Time-to-Digital Converter) for high data rate communication systems using a $0.18{\mu}m$ CMOS process. The coarse-fine architecture has been adopted to improve the resolution of the TDC. A two-stage vernier time amplifier (2S-VTA) was used to amplify the time residue, and the gain of the 2S-VTA was larger than 64. The error during time amplification was compensated using two FTDCs (Fine-TDC) with their outputs. The resolution of the HR-TDC was 0.15 ps with a 12-bit output and the power consumption was 4.32 mW with a 1.8-V supply voltage.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.4
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• pp.269-278
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• 2020

In this paper, two types of DC/DC converters in a hydrogen fuel cell hybrid railway vehicle system, which serve to charge high-voltage battery and supply power to an inverter for driving a driving motor, were compared and analyzed. A two-level interleaving boost converter and a three-level boost converter were compared and analyzed, and a theoretical design method was proposed to have an efficiency characteristic of over 95%. In addition, a digital controller design method considering the digital phase delay component of DSP (TMS320F28335) is presented. Finally, the validity of the theoretical design of the converter with 20kW power was verified through static and dynamic experiments respectively.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.8
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• pp.1544-1550
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• 2009

In this paper, a new single phase voltage sag/swell compensator using direct power conversion is proposed. A new compensator consists of input/output filter, series transformer and direct ac-ac converter, which is a single-phase back-to-back PWM converter without dc-link capacitors. Advantages of the proposed compensator include: simple power circuit by eliminating dc link electrolytic capacitors and thereby, improved reliability and increased life time of the entire compensator; simple PWM strategy or compensating voltage sag/swell at the same time and reduced switching losses in the ac-ac converter. Further, the proposed scheme is able to adopt simple switch commutation method without requiring complex four-step commutation method that is commonly employed in the direct power conversion. Simulation and experimental results are shown to demonstrate the advantages of the new compensator and PWM strategy. A 220V, 3kVA single-phase compensator based on the digital signal processor controller is built and tested.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1833-1842
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• 2016

In grid-connected converter control, grid voltage feedforward is usually introduced to suppress the influence of grid voltage distortion on the converter's grid-side AC current. However, owing to the time-delay in control systems, the suppression effect of the grid voltage distortion is seriously affected. In this paper, the positive effects of the grid voltage feedforward control are analyzed in detail, and the time-delay caused by the low-pass filter (LPF) in the voltage filtering circuits and digital control are summarized. In order to reduce the time-delay effect on the performance of the feedforward control, a voltage feedforward control strategy with time-delay compensation is proposed, in which, a leading correction of the feedforward voltage is used. The optimal leading step used in this strategy is derived from analyzing the phase-frequency characteristics of a LPF and the implementation of digital control. By using the optimal leading step, the delay in the feedforward path can be further counteracted so that the performance of the feedforward control in terms of suppressing the influence of grid voltage distortion on the converter output current can be improved. The validity of the proposed method is verified through simulation and experiment results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.35-40
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• 2005

A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter-the key building blocks of digital PLL (DPLL), there is no need for the 03de-off between jitter, power consumption and silicon area. The DCPLL was implemented in a $0.18\mu$m CMOS process and the active area is 1mm $\times$0.35 mm The DCPLL consumes S9mW during the normal opuation and $984\{mu}W$ during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps ms jitter.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.232-237
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• 2004

In many application of DC-DC converters, loads cannot be specified in advance, i.e., their amplitudes are suddenly changed from the zero to the maximum rating. Generally, design conditions are changed for each load and then each controller is re-designed. Then, a so-called robust DC-DC converter which can cover such extensive load changes and also input voltage changes with one controller is needed. Analog control IC is used usually for the controller of DC-DC converter. Simple integral control etc. are performed with the analog control IC. However it is difficult to retain sufficient robustness of DC-DC converter by these techniques. The authors proposed the method of designing an approximate 2-degree-of-freedom (2DOF) controller of DC-AC converter. This controller has an ability to attain sufficient robustness against extensive load and DC power supply changes. For applying this approximate 2DOF controller to DC-DC converter, it is necessary to improve the degree of approximation for better robustness. In this paper, we propose a method of designing good approximate 2DOF digital controller which makes the control bandwidth wider, and at the same time makes a variation of the output voltage very small at a sudden change of resistive load. The proposed good approximate 2DOF digital controller is actually implemented on a DSP and is connected to a DC-DC converter. Experimental studies demonstrate that this type digital controller can satisfy given specifications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10C
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• pp.1019-1024
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• 2007

In this paper, the 10bit 20MHz pipelined analog-to-digital converter that is able to apply to WLAN system was modeled for ADC design. Each blocks in converter such as sample and hold amplifier(SHA), comparator, multiplyng DAC(MDAC), and digital correction logic(DCL) was modeled. The pipelined ADC with these modeled blocks takes 1/50 less time than the one of simulation using HSPICE.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.414-422
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• 2013

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using a split-capacitor-based differential digital-to-analog converter (DAC). SAR logic and comparator are asynchronously operated to increase the sampling frequency. The time-domain comparator with an offset calibration technique is used to achieve a high resolution. The proposed 10-bit 10-MS/s asynchronous SAR ADC with the area of $140{\times}420{\mu}m^2$ is fabricated using a 0.18-${\mu}m$ CMOS process. Its power consumption is 1.19 mW at 1.8 V supply. The measured SNDR is 49.95 dB for the analog input frequency of 101 kHz. The DNL and INL are +0.57/-0.67 and +1.73/-1.58, respectively.

• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.4
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• pp.1-8
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• 2019

In this paper, we study the BESS of a standalone hybrid street light. The proposed BESS proposed a BESS with the function of efficiently charging irregularly generated power from two or more generators. AC generated by wind power is converted to DC using an AC / DC converter and then to a voltage that can charge the battery through the DC / DC converter. The lack of voltage and current, which is a disadvantage of the MPPT method used in solar power generation, is compensated by the DC value of wind power generation. The compensation method is to convert the DC generated from solar power into a voltage suitable for charging the battery through a DC / DC converter, and then connect the DC generated in wind power in parallel to compensate for the insufficient current to charge the battery in a short time. Allow this to begin. By securing the maximum charging time, the usage time of the stand-alone hybrid street light is huge. Experimental results show that the battery has a short charging time and can be efficiently applied to battery-dependent standalone hybrid street lights.

• Proceedings of the KIEE Conference
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• 2001.04a
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• pp.240-243
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• 2001

This paper presents the digital controller using variable gain for single-phase power factor correction (PFC) converter. Generally, the gain of inner current control loop in single-stage PFC converter has a constant magnitude. This is why input current is distorted under low input voltage. In particular, a digital controller has more time delay than an analog controller which degrades characteristics of control loop. So, it causes the problem that the gain of current control loop isn't increased enough. In addition, the oscillation happens in the peak value of the input voltage open loop PFC system gain changes according to ac input voltage. These aspects make the design of the digital PFC controller difficult. In this paper, the improved digital control method for single-phase power factor converter is presented. The variable gain according to input voltage and input current help to improve current shape. The 800W converter is manufactured to verify the proposed control method.