• Proceedings of the KIEE Conference
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• 2001.05a
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• pp.190-193
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• 2001

In order to verify the efficiency or availability and stability of photovoltaic(PV) generation systems, huge system apparatuses are needed, in general, in which an actual size of solar panel, a type of converter system and some amount of load facilities should be installed in a particular location. It is also hardly possible to compare a Maximum Power Point Tracking (MPPT) control scheme with others under the same weather and load conditions in an actual PV generation system. The only and a possible way to bring above-mentioned problem to be solved is to realize a transient simulation scheme for PV generation systems using real weather conditions such as insolation and surface temperature of solar cell. The authors, in this paper, introduces a novel simulation method, which is based on a real-time digital simulator (RTDS), for PV generation systems under the real weather conditions. Firstly, VI characteristic equation of a solar cell is developed as an empirical formula and reconstructed in the RTDS system, then the real data of weather conditions are interfaced to the analogue inputs of the RTDS. The outcomes of the simulation demonstrate the effectiveness of the proposed simulation scheme in this paper. The results shows that the cost effective verifying for the efficiency or availability and stability of PV generation systems and the comparison research of various control schemes like MPPT under the same real weather conditions are possible.

• Journal of Radiation Protection and Research
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• v.41 no.2
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• pp.81-86
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• 2016

Background: For positron emission tomography (PET) application, cadmium zinc telluride (CZT) has been investigated by several institutes to replace detectors from a conventional system using photomultipliers or Silicon-photomultipliers (SiPMs). The spatial and energy resolution in using CZT can be superior to current scintillator-based state-of-the-art PET detectors. CZT has been under development for several years at the Korea Atomic Energy Research Institute (KAERI) to provide a high performance gamma ray detection, which needs a single crystallinity, a good uniformity, a high stopping power, and a wide band gap. Materials and Methods: Before applying our own grown CZT detectors in the prototype PET system, we investigated preliminary research with a developed discrete type data acquisition (DAQ) system for coincident events at 128 anode pixels and two common cathodes of two CZT detectors from Redlen. Each detector has a $19.4{\times}19.4{\times}6mm^3$ volume size with a 2.2 mm anode pixel pitch. Discrete amplifiers consist of a preamplifier with a gain of $8mV{\cdot}fC^{-1}$ and noise of 55 equivalent noise charge (ENC), a $CR-RC^4$ shaping amplifier with a $5{\mu}s$ peak time, and an analog-to-digital converter (ADC) driver. The DAQ system has 65 mega-sample per second flash ADC, a self and external trigger, and a USB 3.0 interface. Results and Discussion: Characteristics such as the current-to-voltage curve, energy resolution, and electron mobility life-time products for CZT detectors are investigated. In addition, preliminary results of gamma ray imaging using 511 keV of a $^{22}Na$ gamma ray source were obtained. Conclusion: In this study, the DAQ system with a CZT radiation sensor was successfully developed and a PET image was acquired by two sets of the developed DAQ system.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.68-73
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• 2013

In this paper, we proposed a readout circuit of pulse waveform and rate for a U-health system to monitor health condition. For long-time operation without replacing or charging a battery, either pulse waveform or pulse rate is selected as the output data of the proposed readout circuit according to health condition of a user. The proposed readout circuit consists of a simple digital logic discriminator and a dual-mode ADC which operates in the ADC mode or in the count mode. Firstly, the readout circuit counts pulse rate for 4 seconds in the count mode using the dual-mode ADC. Health condition is examined after the counted pulse rate is accumulated for 1 minute in the discriminator. If the pulse rate is out of the preset normal range, the dual-mode ADC operates in the ADC mode where pulse waveform is converted into 10-bit digital data with the sampling frequency of 1 kHz. These data are stored in a buffer and transmitted by 620 kbps to an external monitor through a RF transmitter. The data transmission period of the RF transmitter depends on the operation mode. It is generally 1 minute in the normal situation or 1 ms in the emergency situation. The proposed readout circuit was designed with $0.11{\mu}m$ process technology. The chip area is $460{\times}800{\mu}m^2$. According to measurement, the power consumption is $161.8{\mu}W$ in the count mode and $507.3{\mu}W$ in the ADC mode with the operating voltage of 1 V.

• Journal of the Institute of Convergence Signal Processing
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• v.14 no.4
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• pp.249-254
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• 2013

A fast multiplier and ADC are essential to process the analog signals in real time. The double-base number system(DBNS) is known as an efficient method for this purpose. The DBNS uses the numbers 2 and 3 as the base numbers simultaneously. The system has an advantage of fast multiplication, less chip area, and low power consumption compared to the binary multiplier. However, the inherent errors of the log number's intrinsic tolerance in DBNS are accumulated in a FIR digital filter, so the signal-to-noise ratio(SNR) has a tendency to be degraded. In this paper, the nonlinear encoder of ADC is designed to compensate the accumulated errors of DBNS by analysing the error distributions of various filter coefficients. The new ADC does not sacrifice its own advantages because the encoder circuits are modified only. The experiments were done with an FIR filters those were designed to have -70dB of SNR in stop band. The proposed nonlinear ADC encoder could drop the SNR to -45dB in stop band, in contrast to -35dB with the linear encoder.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.12
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• pp.1641-1647
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• 2018

In this paper, we describe a portable potentiostat which is capable of cyclic voltammetry(CV) and amperometry for electrochemical dissolved oxygen sensor. In addition, this portable potentiostat can also transmit the measured data wirelessly to android devices such as smart phone, tablet, etc. through Bluetooth. The potentiostat system consists of three parts; a voltage generator circuit which is controlled by Arduino nano and 12-bit DAC(digital to analog converter) to generate necessary electric potential for operating the electrochemical sensor, an oxidation/reduction current measurement circuit, and a Bluetooth module to transmit data wirelessly to an android device. Once measurements are carried out with the android application, the measured data is transmitted to the android device via Bluetooth and displayed using the android app. in real time. In this paper, we report the measured reduction current with a fabricated dissolved oxygen sensor in both saturated-oxygen state and zero-oxygen states. The results of the developed portable potentiostat system are in good agreement with those of the commercial portable potentiostat (${\mu}stat200$, Dropsens inc.). The measured peak reduction currents using the developed potentiostat and the commercial ${\mu}stat200$ potentiostat were $-0.755{\mu}A$ and $-0.724{\mu}A$, respectively. The reduction currents measured at zero-oxygen state were $-0.005{\mu}A$ and $-0.004{\mu}A$. The discrepancy between those two systems seems very small, which implies successful development of a portable and wireless potentionstat.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.70-79
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• 2016

This paper proposes a low-power range-scaled 14b 30 MS/s pipeline-SAR composite ADC for high-performance CIS applications. The SAR ADC is employed in the first stage to alleviate a sampling-time mismatch as observed in the conventional SHA-free architecture. A range-scaling technique processes a wide input range of 3.0VP-P without thick-gate-oxide transistors under a 1.8 V supply voltage. The first- and second-stage MDACs share a single amplifier to reduce power consumption and chip area. Moreover, two separate reference voltage drivers for the first-stage SAR ADC and the remaining pipeline stages reduce a reference voltage disturbance caused by the high-speed switching noise from the SAR ADC. The measured DNL and INL of the prototype ADC in a $0.18{\mu}m$ CMOS are within 0.88 LSB and 3.28 LSB, respectively. The ADC shows a maximum SNDR of 65.4 dB and SFDR of 78.9 dB at 30 MS/s, respectively. The ADC with an active die area of $1.43mm^2$ consumes 20.5 mW at a 1.8 V supply voltage and 30 MS/s, which corresponds to a figure-of-merit (FOM) of 0.45 pJ/conversion-step.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.6
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• pp.51-57
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• 2017

In this paper, we designed a frequency synthesizer using DDS (Direct Digital Synthesizer) for Ka-band compact Radar. DDS is applied to generate various waveform and to cover high-speed frequency sweep. In order to reduce size, waveform generator and Ka band frequency up-converter are integrated in one module. Proposed frequency synthesizer provides LFM(Linear Frequency Modulation) waveform and Phase modulated FMCW (Frequency Modulation Continuous Wave) waveform. It is observed that fabricated synthesizer performs $0.191{\mu}sec$ frequency switching time and -89.16 dBc/Hz phase noise at offset 1 kHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.148-158
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• 2012

This paper presents the design of the incremental delta-sigma ADC. The proposed circuit consists of pre-amplifier, S & H circuit, MUX, delta-sigma modulator, and decimation filter. Third-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a $0.18{\mu}m$ CMOS technology. The designed circuit show that the modulator achieves 87.8 dB signal-to-noise and distortion ratio (SNDR) over a 5 kHz signal bandwidth and differential nonlinearity (DNL) of ${\pm}0.25$ LSB, integral nonlinearity (INL) of ${\pm}0.2$ LSB. Power consumption of delta-sigma modulator is $941.6{\mu}W$. It was decided that N cycles are 200 clock for 16-bits output.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.2
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• pp.385-391
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• 2001

In this study, we will develop the sea surface interpretation system that can aware the target in the bottom of the sea. we will setup the database whose records would be the signal patterns of formation about mud, sand, rock and sea shell achieved by using supersonic. then we will convert analog signal received in fish detector to digital one using A/D converter So we can process and analyze this signal pattern then compare it to the one in our Database at the real time to identify the target in the bottom of the sea. After enough times of experiments from the background of the results that have been achieved from many studies(including a water tank experiment and a field investigation), we can aware the exact information of the sediment and the sand in the sea. By analyzing the first, second and third signal of the supersonic characters reflected from the body of a fish categorized by its family and from the body of shellfish, muddy sand, sand and rocks, We will develop the sea surface decipherment system which abstracts the first signal that shows the target in the bottom of the sea and makes the second and third signals filtering.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.10
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• pp.926-934
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• 2016

In this paper, we designed a compact frequency synthesizer with multi-function for Ka-band seeker. DDS(Direct Digital Synthesizer) is applied to generate various waveform and to cover high-speed frequency sweep. In order to reduce size, waveform generator and frequency up-converter are integrated in one module. Proposed frequency synthesizer provides precise detection and tracking waveform for low and high speed targets. It is observed that fabricated synthesizer performs $0.45{\mu}sec$ frequency switching time and -93.69 dBc/Hz phase noise at offset 1 kHz. The size of the synthesizer is kept within 120 mm width, 120 mm length and 22 mm height.