• 대한전자공학회논문지
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• 제24권3호
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• pp.394-399
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• 1987

It is necessary for the speech samples to be stored in memory buffer before speech analyzers without a real time processor process them. In this paper, we propose an algorithm that uses the buffer efficiently, when the analog speech signal is converted to the digital samples by the analog to digital converter. In order to implement this method in real time, the buffer is divided into the starting buffer and the remaining buffer. Until a voiced speech is found, the converted samples are sequentially stored in the starting buffer, and then the buffer is shifted. When a voiced speech is found, the next samples are sequentally recorded in the remaining buffer.

• 한국정밀공학회지
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• 제4권4호
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• pp.25-35
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• 1987

This paper deals with the design of the digital controller for DC servo motor, and it is implemented for the cartesian coordinate 4 axes manipulator. A design method of the controller is adopted an algorithm using the digital position locked loop(DPLL) method and the linear PID control for the smooth motion. To simplify the hardware configuration of control system, 8279 keyboard/display controller, Z-80 CTC counter and 8255 PPI are used. Therefore the design method to control each motor as real-time is presented. To show effectiveness of the design, the PWM circuit and frequency/voltage converter are applied for the velocity control of robot system. When the proposed controller is applied to the 4-axes manipulator, it reveals that the error probabilities of X, Y and Z axis as 0.033%, 0.023% and 0.028% respectively.

• 한국통신학회논문지
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• 제23권9A호
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• pp.2271-2281
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• 1998

The wordlength optimization for the analog-to-digital converter in DS-CDMA receivers is very important for the efficient implementation of front-end digital demodulator blocks. Wideband CDMA systems reqire a very fast acquisition time, thus they prefer the matched filter base dreceiver architecture.However, the matched filter should san very long chips, and as a results, requires a large number of gates and a high-power consumption. In this paper, the quantization effects on the acquisition performance of the matched filter is analyzed stochastically. The quantization is modeled as a series of saturation and digitization procedures, because the distortion due to the saturation is signal dependent and causes very different effects when compared with that of the, random, digitization noise. Numerical results are obtained to show the optimum saturaton limit of the quantizer for a given wordlength. This analysis can give a guide to low-cost and low-powr digital implementations and assurance of the system performance without intensive simulations.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2011년도 제42회 하계학술대회
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• pp.828-829
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• 2011

This paper performs a comparison analysis of two types of HVDC system in Jeju power system. A traditional HVDC transmission system had been composed of line commutated converter based on thyristors and the development of semiconductors enables to apply voltage source converter using IGBTs. The detailed parameters of Jeju power system were considered to make a similar condition with real system in real time digital simulator. Two types of HVDC transmission system were modeled and simulated to compare their characteristics in Jeju power system. The simulation results demonstrate that the VSC-HVDC system has more stable performance due to the fast response speed than LCC-HVDC when the transmission capacity was fluctuated.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.342-348
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• 2015

This paper presents a 1.9-GHz digital ${{\Delta}{\Sigma}}$ fractional-N PLL with a finite impulse response (FIR) filter embedded for noise suppression. The proposed digital implementation of FIR provides a simple method of increasing the number of taps without complicated calculation for gain matching. This work demonstrates 32 tap FIR filtering for the first time and successfully filtered the in-band phase noise generated from delta-sigma modulator (DSM). Design considerations are also addressed to find the optimum number of taps when the resolution of time-to-digital converter (TDC) is given. The PLL, fabricated in $0.11-{\mu}m$ CMOS, achieves a well-regulated in-band phase noise of less than -100 dBc/Hz for the entire range inside the bandwidth of 3 MHz. Compared with the conventional dual-modulus division, the proposed PLL shows an overall noise suppression of about 15dB both at in-band and out-of-band region.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.689-692
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• 1999

This paper describes a 10-bit 75-MHz CMOS current-mode DAC designed for 0.8${\mu}{\textrm}{m}$ double-poly double-metal CMOS technology. This D/A converter is implemented using a current cell matrix that can drive a resistive load without output buffer. In the DAC. a current source is proposed to reduce the linearity error caused by the threshold-voltage variations over a wafer and the glitch energy caused by the time lagging, The integral and differential linearity error are founded to be within $\pm$0.35 LSB and $\pm$0.31 LSB respectively. The maximum conversion rate is about 80 MS/s. The total power dissipation is 160 ㎽ at 75 MS/s conversion rate.

• Journal of Power Electronics
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• 제19권3호
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• pp.613-624
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• 2019

Digital current control techniques are an attractive option for DC-DC converters. In this paper, a digital predictive peak current control algorithm is presented for buck converters that allows the inductor current to track the reference current in two switching cycles. This control algorithm predicts the inductor current in a future period by sampling the input voltage, output voltage and inductor current of the current period, which overcomes the problem of hardware periodic delay. Under the premise of ensuring the stability of the system, the response speed is greatly improved. A real-time parameter identification method is also proposed to obtain the precision coefficient of the control algorithm when the inductance is changed. The combination of the two algorithms achieves adaptive tracking of the peak inductor current. The performance of the proposed algorithms is verified using simulations and experimental results. In addition, its performance is compared with that of a conventional proportional-integral (PI) algorithm.

• 한국인터넷방송통신학회논문지
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• 제17권6호
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• pp.161-167
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• 2017

최근 소형 레이더는 다양한 운용환경에서 대응하기 위하여 소형화와 저전력화를 추진한다. 또한 한번의 타격으로 표적의 시스템을 무능화시키기 위해 높은 거리해상도를 갖는 소형 밀리미터파 레이더 개발을 요구한다. 본 논문에서는 소형 밀리미터파 레이더에서 사용할 수 있는 신호처리기를 설계하고 구현하였다. 소형 밀리미터파 레이더를 위한 신호처리기는 소형화와 저전력화를 위해 디지털 IF(Intermediate Frequency) 수신기와 실시간 FFT 연산이 가능한 DFT(Discrete Fourier Transform) 모듈을 설계하였다. 또한 소형 밀리미터파 레이더의 수신 경로에서 발생할 수 있는 신호의 왜곡을 보정하기 위한 수단으로 FPGA(Field Programmable Gate Array)와 DAC(Digital Analog Converter)를 활용하여 시스템에서 사용하는 RF(Radio Frequency) 신호를 생성할 수 있도록 하였다. 마지막으로 성능시험을 통해 구현한 신호처리기를 검증하였다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1988년도 한국자동제어학술회의논문집(국내학술편); 한국전력공사연수원, 서울; 21-22 Oct. 1988
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• pp.457-461
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• 1988

In this study an one-board micom controlled precision temperature control system has been developed. The digital temperature control system is consisted of an one-board micom as digital controller, a 12-bit A/D and D/A converter, a power amplifier, a NTC thermister, a preamplfier and a heat chamber. An operating control program for the control system was written in Z80 machine language. A Dual-PID predictor control algorithm was proposed. Experments were conducted with different sampling time and limitted error value. As a result, the temperature in a heat chamber can be well controlled within +- 0.2 .deg.C when the sampling time was applied to 10 sec and the limitted error value +- 0.5 .deg.C under the dual-PID predictor control algorithm. By means of one-board micom overall system has been reduced in size and volume, thus the system becomes compact and less expensive.

• 대한의용생체공학회:학술대회논문집
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• 대한의용생체공학회 1997년도 추계학술대회
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• pp.424-427
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• 1997

Electrical impedance plethysmography is still be one of the simplest and most convenient methods or non-invasive measurement of blood low, but it has the weak point can not do real-time measurement because of using chart-record or processing after receiving data from analog plethysmography through A/D converter. In this study. we developed hardware system composed of analog part which include auto-balancing circuit and calibration register and digital part which include 80C196KC, keypad, and LCD. we studied the algorithms or extracting parameter to calculate blood low and implemented it using general purpose micro controller.