• Journal of the Korean Vacuum Society
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• v.8 no.3A
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• pp.249-255
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• 1999

Deposition characteristics of Cu thin films using Ar carrier gas and $H_2$ processing gas at various working pressures and substrate temperatures were investigated. Also, effects of $H_2$ pretreatment using plasma at $200^{\circ}C$ of substrate temperature and 0.6 Torr of chamber pressure were stdied. Cu thin films were deposited on TiN/Si substrate at working pressure of 0.5~1.5 Torr, substrate temperatures of 140~$240^{\circ}C$ with (hface)Cu(tmvs). Substrates were pretreated by $H_2$ plasma, and Cu films deposited in situ using twofold shower head. The purity, electrical resistivity, thickness, surface morphology, optical properties of the deposited Cu films were measured b the AES, four point probe, stylus profiler, SEM,. and the uv-visible spectrophotometer. This study suggests that $H_2$ plasma is an effective method for enhancing deposition rate and for producing high quality copper thin films.

• Journal of the Korean Ceramic Society
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• v.31 no.9
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• pp.981-988
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• 1994

Crystallizable glasses with precipitation of celsian were prepared for the purpose of insulating dielectric layers for the devices such as integrated circuit substrates. Crystallization behavior of these glasses were studied by DTA, SEM, XRD analysis and by the measurement of dielectric properties. The base composition of the glass-ceramic consists in weight percent of 30% SiO2, 10% Al2O3, 26% BaO, 10% CaO, 10% ZnO, 8%TiO2 and 6% B2O3. 2-6 wt% Y2O3 were selected as the nucleating agent to promote monoclinic celsian formation. As a result, in barium-rich glasses containing 4~6wt% Y2O3 , monoclinic celsian was developed as major crystalline phase in the temperature range of 850~90$0^{\circ}C$. Also, the dielectric constant and quality factor of these glass-ceramics were about 9 and more than 1000, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.211-212
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• 2010

GaN 기반의 상부발광형 LED는 동작되는 동안 생기는 전기적 단락, 그리고 칩 위의 p-형 전극과 n-형 전극 사이에 생기는 누설전류 및 신뢰성 확보를 위하여 칩 표면에 passivation 층을 형성하게 된다. SiO2, Si3N4와 같은 passivation layers는 일반적으로 PECVD (Plasma Enhanced Chemical Vapor Deposition)공정을 이용한다, 하지만 이는 공정 특성상 plasma로 인한 damage가 유발되기 때문에 표면 누설 전류가 증가 한다. 이로 인해 forward voltage와 reverse leakage current의 특성이 저하된다. 본 실험에서는 원자층 단위의 박막 증착으로 인해 PECVD보다 단차 피복성이 매우 우수한 PEALD(Plasma Enhanced Atomic Layer Deposition)공정을 이용하여 Al2O3 passivation layer를 증착한 후, 표면 누설전류와 빛의 출력 특성에 대해서 조사해 보았다. PSS (patterned sapphire substrate) 위에 성장된 LED 에피구조를 사용하였고, TCP(Trancformer Copled Plasma)장비를 사용하여 에칭 공정을 진행하였다. 이때 투명전극을 증착하기 위해 e-beam evaporator를 사용하여 Ni/Au를 각각 $50\;{\AA}$씩 증착한 후 오믹 특성을 향상시키기 위하여 $500^{\circ}C$에서 열처리를 해주었다. 그리고 Ti/Au($300/4000{\AA}$) 메탈을 사용하여 p-전극과 n-전극을 형성하였다. Passivation을 하지 않은 경우에는 reverse leakage current가 -5V 에서 $-1.9{\times}10-8$ A 로 측정되었고, SiO2와 Si3N4을 passivation으로 이용한 경우에는 각각 $8.7{\times}10-9$과 $-2.2{\times}10-9$로 측정되었다. Fig. 1 에서 보면 알 수 있듯이 5 nm의 Al2O3 film을 passivation layer로 이용할 경우 passivation을 하지 않은 경우를 제외한 다른 passivation 경우보다 reverse leakage current가 약 2 order ($-3.46{\times}10-11$ A) 정도 낮게 측정되었다. 그 이유는 CVD 공정보다 짧은 ALD의 공정시간과 더 낮은 RF Power로 인해 plasma damage를 덜 입게 되어 나타난 것으로 생각된다. Fig. 2 에서는 Al2O3로 passivation을 한 소자의 forward voltage가 SiO2와 Si3N4로 passivation을 한 소자보다 각각 0.07 V와 0.25 V씩 낮아지는 것을 확인할 수 있었다. 또한 Fig. 3 에서는 Al2O3로 passivation을 한 소자의 output power가 SiO2와 Si3N4로 passivation을 한 소자보다 각각 2.7%와 24.6%씩 증가한 것을 볼 수 있다. Output power가 증가된 원인으로는 향상된 forward voltage 및 reverse에서의 leakage 특성과 공기보다 높은 Al2O3의 굴절률이 광출력 효율을 증가시켰기 때문인 것으로 판단된다.

• Korean Journal of Materials Research
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• v.19 no.1
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• pp.28-32
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• 2009

Silicon carbide (SiC) is a promising material for power device applications due to its wide band gap (3.26 eV for 4H-SiC), high critical electric field and excellent thermal conductivity. The Schottky barrier diode is the representative high-power device that is currently available commercially. A field plate edge-terminated 4H-SiC was fabricated using a lift-off process for opening the Schottky contacts. In this case, Ni/Ti dual-metal contacts were unintentionally formed at the edge of the Schottky contacts and resulted in the degradation of the electrical properties of the diodes. The breakdown voltage and Schottky barrier height (SBH, ${\Phi}_B$) was 107 V and 0.67 eV, respectively. To form homogeneous single-metal Ni/4H-SiC Schottky contacts, a deposition and etching method was employed, and the electrical properties of the diodes were improved. The modified SBDs showed enhanced electrical properties, as witnessed by a breakdown voltage of 635 V, a Schottky barrier height of ${\Phi}_B$=1.48 eV, an ideality factor of n=1.04 (close to one), a forward voltage drop of $V_F$=1.6 V, a specific on resistance of $R_{on}=2.1m{\Omega}-cm^2$ and a power loss of $P_L=79.6Wcm^{-2}$.

• Korean Journal of Materials Research
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• v.12 no.3
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• pp.211-214
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• 2002

Properties of 52/48 PZT films with various thicknesses for piezoelectric micro-electro mechanical systems (MEMS) devices fabricated by multi-coating method on $Pt(3500{\AA})/Ti(400{\AA})/SiO_2(3000{\AA})/Si$(525$\mu\textrm{m}$) substrates were investigated. PZT films were deposited by spin-coating process at 3500 rpm for 30 sec, followed by pyrolysis at 45$0^{\circ}C$ for 10 min producing the thickness of about 120nm. These processes were repeated 4, 8, 12, 16 and 20 times in order to have various thicknesses, respectively. Finally, they were crystallized at $650^{\circ}C$ for 30 min. All thick PZT films showed dense and homogeneous surface microstructures. Thick PZT films showed crystalline structures of random orientations with increasing thickness. Dielectric constants of thick PZT films were increased with increasing film thickness and reached 800 at 100kHz for 2.3$\mu\textrm{m}$ thick PZT film. $P_r\; and\; E_c$ of 2.3$\mu\textrm{m}$ thick PZT films were about 20$\mu$C/$\textrm{cm}^2$ and 63kV/cm. Depth profile analysis by Auger Electron Spectroscopy (AES) of 4800 $\AA$ thick PZT film showed the formation of the perovskite phase on Pt layer by Pb diffusion behavior. It was considered that Pb-Pt intermediate layer promoted PZT (111) columnar structures.

• Journal of the Korean Ceramic Society
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• v.28 no.9
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• pp.675-682
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• 1991

Among many problems that need to be solved in the process of preparing multilayer chip LC filters, we studied the control of shrinkage in order to prevent the crack, warpage, and/or delamination which occurs at the interface between the inductance (L part) and the capacitance (C part). Shrinkage was controlled by compositions, powder size, calcining temperature and amount of organic binder. Capacitance sheet was prepared by mixing 65 wt% binder with the composition of 96 wt% TiO2 having an average particle size of 0.5 $\mu\textrm{m}$, 3 wt% CuO. After small amount of MnO2 and SiO2 added, it was calcined at 750$^{\circ}C$ for 2 hr. Inductance sheet was prepared by mixing 60 wt% binder with the composition of 49.5% mol% Fe2O3, 20.5 mol% ZnO, 20 mol% NiO and 10 mol% CuO which was calcined at 775$^{\circ}C$ for 2 hr. These sheets was laminated at 250 kg/$\textrm{cm}^2$, and cofired at 900$^{\circ}C$ for 2 hr to give rise to a multilayer chip LC filter without any warpage.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.399-399
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• 2013

Metal silicides는 Si 기반의microelectronic devices의 interconnect와 contact 물질 등에 사용하기 위하여 그 형성 mechanism과 전기적 특성에 대한 연구가 많이 이루어지고 있다. 이 중 Rare-earth(RE) silicides는 저온에서 silicides를 형성하고, n-type Si과 낮은 Schottky Barrier contact (~0.3 eV)을 이룬다. 또한 낮은 resistivity와 Si과의 작은 lattice mismatch, 그리고 epitaxial growth의 가능성, 높은 thermal stability 등의 장점을 갖고 있다. RE silicides 중 ytterbium silicide는 가장 낮은 electric work function을 갖고 있어 n-channel schottky barrier MOSFETs의 source/drain으로 주목받고 있다. 또한 Silicon 기반의 CMOSFETs의 성능 향상 한계로 인하여 germanium 기반의 소자에 대한 연구가 이루어져 왔다. Ge 기반 FETs 제작을 위해서는 낮은 source/drain series/contact resistances의 contact을 형성해야 한다. 본 연구에서는 저접촉 저항 contact material로서 ytterbium germanide의 가능성에 대해 고찰하고자 하였다. HRTEM과 EDS를 이용하여 ytterbium germanide의 미세구조 분석과 면저항 및 Schottky Barrier Heights 등의 전기적 특성 분석을 진행하였다. Low doped n-type Ge (100) wafer를 1%의 hydrofluoric (HF) acid solution에 세정하여 native oxide layer를 제거하고, 고진공에서 RF sputtering 법을 이용하여 ytterbium 30 nm를 먼저 증착하고, 그 위에 ytterbium의 oxidation을 방지하기 위한 capping layer로 100 nm 두께의 TiN을 증착하였다. 증착 후, rapid thermal anneal (RTA)을 이용하여 N2 분위기에서 $300{\sim}700^{\circ}C$에서 각각 1분간 열처리하여 ytterbium germanides를 형성하였다. Ytterbium germanide의 미세구조 분석은 transmission electron microscopy (JEM-2100F)을 이용하였다. 면 저항 측정을 위해 sulfuric acid와 hydrogen peroxide solution (H2SO4:H2O2=6:1)에서 strip을 진행하여 TiN과 unreacted Yb을 제거하였고, 4-point probe를 통하여 측정하였다. Yb germanides의 면저항은 열처리 온도 증가에 따라 감소하다 증가하는 경향을 보이고, $400{\sim}500^{\circ}C$에서 가장 작은 면저항을 나타내었다. HRTEM 분석 결과, deposition 과정에서 Yb과 Si의 intermixing이 일어나 amorphous layer가 존재하였고, 열처리 온도가 증가하면서 diffusion이 더 활발히 일어나 amorphous layer의 두께가 증가하였다. $350^{\circ}C$ 열처리 샘플에서 germanide/Ge interface에서 epitaxial 구조의 crystalline Yb germanide가 형성되었고, EDS 측정 및 diffraction pattern을 통하여 안정상인 YbGe2-X phase임을 확인하였다. 이러한 epitaxial growth는 면저항의 감소를 가져왔으며, 열처리 온도가 증가하면서 epitaxial layer가 증가하다가 고온에서 polycrystalline 구조의 Yb germanide가 형성되어 면저항의 증가를 가져왔다. Schottky Barrier Heights 측정 결과 또한 면저항 경향과 동일하게 열처리 증가에 따라 감소하다가 고온에서 다시 증가하였다.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.3
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• pp.1-6
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• 2002

A low temperature process technology of copper thin films has been developed by a chemical vapor deposition technology for multi-level metallzations in ULSI fabrication. The copper films were deposited on TiN/Si substrates in helium atmosphere with the substrate temperature between $130^{\circ}C$ and $250^{\circ}C$. In order to get more reliable metallizations, effects on the post-annealing treatment to the electrical properties of the copper films have been investigated. The Cu films were annealed at the $5 \times10^{-6}$ Torr vacuum condition and the electrical resistivity and the nano-structures were measured for the Cu films. The electrical resistivity of Cu films shown to be reduced by the post-annealing. The electrical resistivity of 2.0 $\mu \Omega \cdot \textrm{cm}$ was obtained for the sample deposited at the substrate temperature of $180^{\circ}C$ after vacuum annealed at $300^{\circ}C$. The resistivity variations of the films was not exactly matched with the size of the nano-structures of the copper grains, but more depended on the contamination of the copper films.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.4
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• pp.312-317
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• 2000

Ferroelectric S $r_{0.9}$/B $i_{2.1}$/T $a_{2}$/ $O_{9}$ solutions were synthesized using sol-gel process in which strontinum ethoxide bismuth ethoxide trantalum ethoxide were used a s startring materials. SBT thin films were coated on Pt/Ti/ $SiO_2$/Si substrates by spin-coating. rapid thermal annealing (RTA) was used to promote crystallization. Thin films were annealed at $700^{\circ}C$ for 1 hr in an oxygen atmosphere. This temperature is about 10$0^{\circ}C$ lower than the usual annealing temperature for SBT thin films. Pt top-electrode was deposited by sputtering and thin films were post-annealed at $700^{\circ}C$ for 30 min. to enhance electrical properties. As the RTA temperature increased the higher 2 $P_{r}$ values were obtained. At RTA temperature being 78$0^{\circ}C$ remanent polarization of S $r_{0.9}$/B $i_{2.1}$/T $a_{2}$/ $O_{9}$ thin film was 7.73 $\mu$C/cm $_2$ and the leakage current density was 1.14$\times$10$^{-7}$ A/c $m^2$ at 3 V. As RTA temperature increased the breakdown voltage was decreased. It is considered that the low-field breadown is caused by the rough surface of SBT films and forming bismuth metal in SBT thin films.films.lms.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.115-118
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• 2000

Uncooled pyroelectric infrared detectors based on BST(B $a_{-x}$S $r_{x}$Ti $O_3$) thin films have been fabricated by RF magnetron sputtering and surface Micromachining technology. The detectors form BST thin film ferroelectric capacitors grown by RF magnetron sputtering on N/O/N(S $i_3$ $N_4$/ $SiO_2$/S $i_3$ $N_4$) membrane. The sputtered BST thin film exhibits highly c-axis oriented crystal structure that no poling treatment for sensing applications is required. This is an essential factor to increase the yield for realization of an infrared image sensor. surface-Micromachining technology is used to lower the thermal mass of the detector by giving maximum sensor efficiency Gold-black is evaporated on top of the sensing elements used the thermal evaporator. fabricated uncooled pyroelectric infrared detectors is highly output voltage at the low temperature(1$^{\circ}C$).).).