• Proceedings of the Korean Vacuum Society Conference
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• 1997.07a
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• pp.34-34
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• 1997

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.430-430
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• 2008

열화학기상 증착법으로 2원계 합금인 Invar 36(63wt% Fe, 37wt% Ni)을 이용하여 다중벽 탄소나노튜브를 360도의 저온에서 까지 합성이 가능함을 확인하였다. 촉매와 Si 기판과의 silicide형성을 막기 위한 Ti층의 두께가 증가함에 따라서 탄소나노튜브의 길이가 잘 자라는 것을 확인하였으며, 미량의 물이 첨가 되었을 경우 탄소나노튜브의 길이 성장에 큰 변화가 있음을 확인하였다. 또한 물을 포함하는 실험에서는 촉매인 Invar36의 두께가 0.5 nm 일 때에 비하여 0.25 nm 두께에서 물에 대한 영향이 더 크게 나타남을 SEM 사진을 통해 확인할 수 있었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.11a
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• pp.242-245
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• 1997

Co single layer and Co/Ti used to form a CoSi$_2$ contact. We fabricated the n+/p diodes with this CoSi$_2$ contact as diffusion source of As. The diodes wish CoSi$_2$ formed by Co/ri bilayer had more Bo7d electrical characteristics than CoSi$_2$ formed by Co single layer. This shows that the flatness of interface which is a parameters to affect the diodes\` electrical characteristics. And the electrical characteristics of diodes are more good when the second thermal activation processing temperature was low as much as 50$0^{\circ}C$ than the temperature high over than 80$0^{\circ}C$, it was thought as that the silicide was degradated at high temperature.

• Proceedings of the Korea Crystallographic Association Conference
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• 2002.11a
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• pp.42-43
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• 2002

반도체 디바이스의 발전은 높은 직접화 및 동작 속도를 추구하고 있으며, 이를 위해서 MOSFET의 scale down시 발생되는 문제를 해결해야만 한다. 특히, Channel이 짧아짐으로써 발생하는 device의 열화현상으로 동작전압의 조절이 어려워 짐을 해결해야만 하며, gate oxide 두께를 줄임으로써 억제할 수 있다고 알려져 왔다. 현재, gate oxide으로 사용되고 있는 SiO2박막은 비정질로써 ～8.7 eV의 높은 band gap과 Si기판 위에서 성장이 용이하며 안정하다는 장점이 있으나, 두께가 1.6 nm 이하로 얇아질 경우 전자의 direct Tunneling에 의한 leakage current 증가와 gate impurity인 Boron의 channel로의 확산, 그리고 poly Si gate의 depletion effect[1,2] 등의 문제점으로 더 이상 사용할 수 없게 된다. 2001년 ITRS에 의하면 ASIC제품의 경우 2004년부터 0.9～l.4 nm 이하의 EOT가 요구된다고 발표하였다. 따라서, gate oxide의 물리적인 두께를 증가시켜 전자의 Tunneling을 억제하는 동시에 유전막에 걸리는 capacitance를 크게 할 수 있다는 측면에서 high-k 재료를 적용하기 위한 연구가 진행되고 있다[3]. High-k 재료로 가능성 있는 절연체들로는 A1₂O₃, Y₂O₃, CeO₂, Ta₂O, TiO₂, HfO₂, ZrO₂,STO 그리고 BST등이 있으며, 이들 재료 중 gate oxide에 적용하기 위해 크게 두 가지 측면에서 고려해야 하는데, 첫째, Si과 열역학적으로 안정하여 후속 열처리 공정에서 계면층 형성을 배제하여야 하며 둘째, 일반적으로 high-k 재료들은 유전상수에 반비례하는 band gap을 갖는 것으로 알려줘 있는데 이 Barrier Height에 지수적으로 의존하는 leakage current때문에 절연체의 band gap이 낮아서는 안 된다는 점이다. 최근 20이상의 유전상수와 ～5 eV 이상의 Band Gap을 가지며 Si기판과 열역학적으로 안정한 ZrO₂[4], HfiO₂[5]가 관심을 끌고 있다. HfO₂은 ～30의 고유전상수, ～5.7 eV의 높은 band gap, 실리콘 기판과의 열역학적 안전성 그리고 poly-Si와 호환성등의 장점으로 최근 많이 연구가 진행되고 있다. 또한, Hf은 SiO₂를 환원시켜 HfO₂가 될 수 있으며, 다른 silicide와 다르게 Hf silicide는 쉽게 산화될 수 있는 점이 보고되고 있다.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2007.06a
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• pp.193-198
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• 2007

The NiSi is very promising candidate for the metallization in 60nm CMOS process such as FUSI(fully silicided) gate and source/drain contact because it exhibits non-size dependent resistance, low silicon consumption and mid-gap workfunction. Ni film was first deposited by using ALD (atomic layer deposition) technique with Bis-Ni precursor and $H_2$ reactant gas at $220^{\circ}C$ with deposition rate of $1.25{\AA}/cycle$. The as-deposited Ni film exhibited a sheet resistance of $5{\Omega}/{\square}$. RTP (repaid thermal process) was then performed by varying temperature from $400^{\circ}C$ to $900^{\circ}C$ in $N_2$ ambient for the formation of NiSi. The process window temperature for the formation of low-resistance NiSi was estimated from $600^{\circ}C$ to $800^{\circ}C$ and from $700^{\circ}C$ to $800^{\circ}C$ with and without Ti capping layer. The respective sheet resistance of the films was changed to $2.5{\Omega}/{\square}$ and $3{\Omega}/{\square}$ after silicidation. This is because Ti capping layer increases reaction between Ni and Si and suppresses the oxidation and impurity incorporation into Ni film during silicidation process. The NiSi films were treated by additional thermal stress in a resistively heated furnace for test of thermal stability, showing that the film heat-treated at $800^{\circ}C$ was more stable than that at $700^{\circ}C$ due to better crystallinity.

• Journal of the Semiconductor & Display Technology
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• v.6 no.3
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• pp.19-23
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• 2007

The NiSi is very promising candidate for the metallization in 45 nm CMOS process such as FUSI(fully silicided) gate and source/drain contact because it exhibits non-size dependent resistance, low silicon consumption and mid-gap workfunction. Ni film was first deposited by using ALD (atomic layer deposition) technique with Bis-Ni precursor and $H_2$ reactant gas at $220^{\circ}C$ with deposition rate of $1.25\;{\AA}/cycle$. The as-deposited Ni film exhibited a sheet resistance of $5\;{\Omega}/{\square}$. RTP (repaid thermal process) was then performed by varying temperature from $400^{\circ}C$ to $900^{\circ}C$ in $N_2$ ambient for the formation of NiSi. The process temperature window for the formation of low-resistance NiSi was estimated from $600^{\circ}C$ to $800^{\circ}C$ and from $700^{\circ}C$ to $800^{\circ}C$ with and without Ti capping layer. The respective sheet resistance of the films was changed to $2.5\;{\Omega}/{\square}$ and $3\;{\Omega}/{\square}$ after silicidation. This is because Ti capping layer increases reaction between Ni and Si and suppresses the oxidation and impurity incorporation into Ni film during silicidation process. The NiSi films were treated by additional thermal stress in a resistively heated furnace for test of thermal stability, showing that the film heat-treated at $800^{\circ}C$ was more stable than that at $700^{\circ}C$ due to better crystallinity.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.444-445
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• 2009

The metallic contact system of silicon solar cell must have several properties, such as low contact resistance, easy application and good adhesion. Ni is shown to be a suitable barrier to Cu diffusion as well as desirable contact metal to silicon. Nickel monosilicide(NiSi) has been suggested as a suitable silicide due to its lower resistivity, lower sintering temperature and lower layer stress than $TiSi_2$. Copper and Silver can be plated by electro & light-induced plating method. Light-induced plating makes use the photovoltaic effect of solar cell to deposit the metal on the front contact. The cell is immersed into the electrolytic plating bath and irradiated at the front side by light source, which leads to a current density in the front side grid. Electroless plated Ni/ Electro&light-induced plated Cu/ Light-induced plated Ag contact solar cells result in an energy conversion efficiency of 16.446 % on $0.2\sim0.6\;{\Omega}{\cdot}cm$, $20\;\times\;20\;mm^2$, CZ(Czochralski) wafer.

• New & Renewable Energy
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• v.1 no.1 s.1
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• pp.37-43
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• 2005

High-efficiency silicon solar cells have potential applications on mobile electronics and electrical vehicles. The fabrication processes of the high efficiency cells necessitate com placated fabrication precesses and expensive materials. Ti/Pd/Ag metal contact has been used only for limited area In spite of good stability and low contact resistance because of Its expensive material cost and precesses. Screen printed contact formed by Ag paste causes a low fill factor and a high shading loss of commercial solar cells because of high contact resistance and a low aspect ratio. Low cost Ni/Cu metal contact has been formed by using a low cost electroless and electroplating. Nickel silicide formation at the interface enhances stability and reduces the contact resistance resulting In an energy conversion efficiency of $20.2\%\;on\;0.50{\Omega}cm$ FZ wafer. Tapered contact structure has been applied to large area solar cells with $6.7\times6.7cm^2$ in order to reduce power losses by the front contact The tapered front metal contact Is easily formed by the electroplating technique producing $45cm^2$ solar cells with an efficiency of $21.4\%$ on $21.4\%\;on\;2{\Omega}cm$ FZ wafer.

• Korean Journal of Materials Research
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• v.8 no.9
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• pp.791-796
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• 1998

self-aligned silicide(salicide)제조시 CoSi2의 에피텍셜 성장을 돕기 위하여 Co와 Si 사이에 내열금속층을 넣은 Co/내열금속/Si의 실리사이드화가 관심을 끌고 있다. Hf 역시 Ti와 마찬가지로 이러한 용도로 사용될 수 있다. 한편, Co/Hf 이중층 salicide 트랜지스터가 성공적으로 만들어지기 위해서는 spacer oxide 위에 증착된 Co/Hf 이중층이 열적으로 안정해야 한다. 이러한 배경에서 본 연구에서는 SiO2기판 위에 증착한 Co 단일층과 Co/Hf 이중층을 급속열처리할 때 Co와 SiO2간의 계면과 Co/Hf와 SiO2간의 계면에서의 상호반응에 대하여 조사하였다. Co 단일층과 Co/Hf 이중층은 각각 $500^{\circ}C$와 $550^{\circ}C$에서 열처리한 후 면저항이 급격하게 증가하기 시작하였는데, 이것은 Co층이 SiO2와의 계면에너지를 줄이기 위하여 응집되기 때문이다. 이 때 Co/Hf의 경우 열처리후 Hf에 의하여 SiO2 기판이 일부 분해됨으로써 Hf 산화물이 형성되었으나, 전도성이 있는 HfSix 등의 화합물은 발견되지 않았다.

• Korean Journal of Materials Research
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• v.9 no.2
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• pp.199-204
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• 1999

As the engine design change to get high efficiency and performance of commercial diesel engine, surface wear of the cam follower becomes an important issues as applied load increasing at the contact face between cam follower and cam. Purpose of this study is the developing of the ceramic cam follower made of silicon nitride ceramic which is more wear resistant than the cast iron and sintered cam follower. Ceramic cam follower was made by direct brazing of thin ceramic disk to steel can follower body using active bracing alloy. Effect of joining condition on the interfacial phases and joining strength wer examined at bvarious joining temperatures, times, and cooling rates. Crowning resulted from the difference of thermal expansion coefficient after direct brazing without using any stress-relieving inter layer was measured. Interfacial phases are mainly titanium silicide and titanium nitride which are the products between active metal(Ti) in brazing alloy and silicon nitiride. Maximum joining strength of the ceramic metal joint, measured by DBS method, was 334MPa. Crowning(R) of the prototype ceramic cam follower was 1595mm. As machining for crowning is not necessary, production cost can be reduced.